[PATCH v1 1/1] Support YUV422 for DPTX.
Liankun Yang
liankun.yang at mediatek.com
Thu May 9 19:15:29 PDT 2024
Adjust the training sequence.Detects the actual link condition
and calculates the bandwidth where the relevant resolution resides.
The bandwidth is recalculated and modes that exceed the bandwidth are
filtered.
Example Modify bandwidth filtering requirements.
Signed-off-by: Liankun Yang <liankun.yang at mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dp.c | 81 ++++++++++++++++++-------------
1 file changed, 46 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index 2136a596efa1..3e645bd6fe27 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -66,6 +66,13 @@ enum {
MTK_DP_CAL_MAX,
};
+enum mtk_dp_color_format {
+ MTK_DP_COLOR_FORMAT_RGB = 0,
+ MTK_DP_COLOR_FORMAT_YUV422 = 0x1,
+ MTK_DP_COLOR_FORMAT_YUV444 = 0x2,
+ MTK_DP_COLOR_FORMAT_YUV420 = 0x3,
+};
+
struct mtk_dp_train_info {
bool sink_ssc;
bool cable_plugged_in;
@@ -84,7 +91,7 @@ struct mtk_dp_audio_cfg {
};
struct mtk_dp_info {
- enum dp_pixelformat format;
+ enum mtk_dp_color_format format;
struct videomode vm;
struct mtk_dp_audio_cfg audio_cur_cfg;
};
@@ -457,7 +464,7 @@ static void mtk_dp_set_msa(struct mtk_dp *mtk_dp)
}
static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
- enum dp_pixelformat color_format)
+ enum mtk_dp_color_format color_format)
{
u32 val;
@@ -467,10 +474,10 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
DP_TEST_COLOR_FORMAT_MASK);
switch (color_format) {
- case DP_PIXELFORMAT_YUV422:
+ case MTK_DP_COLOR_FORMAT_YUV422:
val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422;
break;
- case DP_PIXELFORMAT_RGB:
+ case MTK_DP_COLOR_FORMAT_RGB:
val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB;
break;
default:
@@ -1322,7 +1329,7 @@ static void mtk_dp_initialize_priv_data(struct mtk_dp *mtk_dp)
mtk_dp->train_info.lane_count = mtk_dp->max_lanes;
mtk_dp->train_info.cable_plugged_in = plugged_in;
- mtk_dp->info.format = DP_PIXELFORMAT_RGB;
+ mtk_dp->info.format = MTK_DP_COLOR_FORMAT_YUV422;
memset(&mtk_dp->info.vm, 0, sizeof(struct videomode));
mtk_dp->audio_enable = false;
}
@@ -1371,7 +1378,7 @@ static void mtk_dp_sdp_set_down_cnt_init_in_hblank(struct mtk_dp *mtk_dp)
drm_display_mode_from_videomode(vm, &mode);
- pix_clk_mhz = mtk_dp->info.format == DP_PIXELFORMAT_YUV420 ?
+ pix_clk_mhz = mtk_dp->info.format == MTK_DP_COLOR_FORMAT_YUV420 ?
mode.clock / 2000 : mode.clock / 1000;
switch (mtk_dp->train_info.lane_count) {
@@ -1870,6 +1877,7 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
struct mtk_dp *mtk_dp = dev;
unsigned long flags;
u32 status;
+ int ret;
if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in)
msleep(100);
@@ -1888,9 +1896,28 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
memset(&mtk_dp->info.audio_cur_cfg, 0,
sizeof(mtk_dp->info.audio_cur_cfg));
+ mtk_dp->enabled = false;
+ /* power off aux */
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
+ DP_PWR_STATE_BANDGAP_TPLL,
+ DP_PWR_STATE_MASK);
+
mtk_dp->need_debounce = false;
mod_timer(&mtk_dp->debounce_timer,
jiffies + msecs_to_jiffies(100) - 1);
+ } else {
+ mtk_dp_aux_panel_poweron(mtk_dp, true);
+
+ ret = mtk_dp_parse_capabilities(mtk_dp);
+ if (ret)
+ drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
+
+ /* Training */
+ ret = mtk_dp_training(mtk_dp);
+ if (ret)
+ drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
+
+ mtk_dp->enabled = true;
}
}
@@ -2057,16 +2084,6 @@ static struct edid *mtk_dp_get_edid(struct drm_bridge *bridge,
new_edid = drm_get_edid(connector, &mtk_dp->aux.ddc);
- /*
- * Parse capability here to let atomic_get_input_bus_fmts and
- * mode_valid use the capability to calculate sink bitrates.
- */
- if (mtk_dp_parse_capabilities(mtk_dp)) {
- drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
- kfree(new_edid);
- new_edid = NULL;
- }
-
if (new_edid) {
struct cea_sad *sads;
@@ -2243,14 +2260,10 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge,
return;
}
- mtk_dp_aux_panel_poweron(mtk_dp, true);
-
- /* Training */
- ret = mtk_dp_training(mtk_dp);
- if (ret) {
- drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
- goto power_off_aux;
- }
+ /* power on aux */
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
+ DP_PWR_STATE_BANDGAP_TPLL_LANE,
+ DP_PWR_STATE_MASK);
ret = mtk_dp_video_config(mtk_dp);
if (ret)
@@ -2310,12 +2323,11 @@ mtk_dp_bridge_mode_valid(struct drm_bridge *bridge,
{
struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
u32 bpp = info->color_formats & DRM_COLOR_FORMAT_YCBCR422 ? 16 : 24;
- u32 rate = min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) *
- drm_dp_max_lane_count(mtk_dp->rx_cap),
- drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) *
- mtk_dp->max_lanes);
+ u32 lane_count_min = mtk_dp->train_info.lane_count;
+ u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
+ lane_count_min;
- if (rate < mode->clock * bpp / 8)
+ if (rate * 97 / 100 < (mode->clock * bpp / 8))
return MODE_CLOCK_HIGH;
return MODE_OK;
@@ -2356,10 +2368,9 @@ static u32 *mtk_dp_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
struct drm_display_info *display_info =
&conn_state->connector->display_info;
- u32 rate = min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) *
- drm_dp_max_lane_count(mtk_dp->rx_cap),
- drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) *
- mtk_dp->max_lanes);
+ u32 lane_count_min = mtk_dp->train_info.lane_count;
+ u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
+ lane_count_min;
*num_input_fmts = 0;
@@ -2406,9 +2417,9 @@ static int mtk_dp_bridge_atomic_check(struct drm_bridge *bridge,
bridge_state->output_bus_cfg.format);
if (input_bus_format == MEDIA_BUS_FMT_YUYV8_1X16)
- mtk_dp->info.format = DP_PIXELFORMAT_YUV422;
+ mtk_dp->info.format = MTK_DP_COLOR_FORMAT_YUV422;
else
- mtk_dp->info.format = DP_PIXELFORMAT_RGB;
+ mtk_dp->info.format = MTK_DP_COLOR_FORMAT_RGB;
if (!crtc) {
drm_err(mtk_dp->drm_dev,
--
2.18.0
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