[PATCH] clk: rockchip: rk3568: Add PLL rate for 724 MHz

[Heiko Stuebner]

On Fri, 3 May 2024 17:33:29 +0200, Lucas Stach wrote:
> This rate allows to provide a low-jitter 72,4 MHz pixelclock
> for a custom eDP panel from the VPLL.
> 
> 

Applied, thanks!

[1/1] clk: rockchip: rk3568: Add PLL rate for 724 MHz
      commit: f513991b69885025995dcb4ca75d2ee7261e1273

Best regards,
-- 
Heiko Stuebner <heiko at sntech.de>