[PATCH 2/3] KVM: arm64: Don't pass a TLBI level hint when zapping table entries

Will Deacon will at kernel.org
Tue Mar 26 02:34:16 PDT 2024


On Tue, Mar 26, 2024 at 01:37:43AM -0700, Oliver Upton wrote:
> On Mon, Mar 25, 2024 at 06:51:57PM +0000, Will Deacon wrote:
> > The TLBI level hints are for leaf entries only, so take care not to pass
> > them incorrectly after clearing a table entry.
> > 
> > Cc: Gavin Shan <gshan at redhat.com>
> > Cc: Marc Zyngier <maz at kernel.org>
> > Cc: Quentin Perret <qperret at google.com>
> > Fixes: 82bb02445de5 ("KVM: arm64: Implement kvm_pgtable_hyp_unmap() at EL2")
> > Fixes: 6d9d2115c480 ("KVM: arm64: Add support for stage-2 map()/unmap() in generic page-table")
> > Signed-off-by: Will Deacon <will at kernel.org>
> > ---
> >  arch/arm64/kvm/hyp/pgtable.c | 12 +++++++-----
> >  1 file changed, 7 insertions(+), 5 deletions(-)
> > 
> > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
> > index de0b667ba296..a40dafc43bb6 100644
> > --- a/arch/arm64/kvm/hyp/pgtable.c
> > +++ b/arch/arm64/kvm/hyp/pgtable.c
> > @@ -528,7 +528,7 @@ static int hyp_unmap_walker(const struct kvm_pgtable_visit_ctx *ctx,
> >  
> >  		kvm_clear_pte(ctx->ptep);
> >  		dsb(ishst);
> > -		__tlbi_level(vae2is, __TLBI_VADDR(ctx->addr, 0), ctx->level);
> > +		__tlbi_level(vae2is, __TLBI_VADDR(ctx->addr, 0), TLBI_TTL_UNKNOWN);
> >  	} else {
> >  		if (ctx->end - ctx->addr < granule)
> >  			return -EINVAL;
> > @@ -896,10 +896,12 @@ static void stage2_unmap_put_pte(const struct kvm_pgtable_visit_ctx *ctx,
> >  	if (kvm_pte_valid(ctx->old)) {
> >  		kvm_clear_pte(ctx->ptep);
> >  
> > -		if (!stage2_unmap_defer_tlb_flush(pgt) ||
> > -		    kvm_pte_table(ctx->old, ctx->level)) {
> > -			kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu,
> > -					ctx->addr, ctx->level);
> > +		if (kvm_pte_table(ctx->old, ctx->level)) {
> > +			kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu, ctx->addr,
> > +				     TLBI_TTL_UNKNOWN);
> 
> Ah, here it is! Can you add this invalidation to patch #1? Otherwise the
> fix will intermediately introduce another bug, AFAICT.

Heh, well I'd argue that bug already exists in the case that TLB
invalidation isn't deferred, so that's why I kept them separate.

But happy to fold in if you prefer. Main thing is to get it fixed!

Will



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