[PATCH] iommu/arm-smmu-v3: Fix access for STE.SHCFG

[Jason Gunthorpe]

On Sat, Mar 23, 2024 at 01:46:58PM +0000, Mostafa Saleh wrote:
> STE attributes(NSCFG, PRIVCFG, INSTCFG) use value 0 for "Use Icomming",
> for some reason SHCFG doesn't follow that, and it is defined as "0b01".
> 
> Currently the driver sets SHCFG to Use Incoming for stage-2 and bypass
> domains.
> 
> However according to the User Manual (ARM IHI 0070 F.b):
> 	When SMMU_IDR1.ATTR_TYPES_OVR == 0, this field is RES0 and the
> 	incoming Shareability attribute is used.
> 
> This patch adds a condition for writing SHCFG to Use incoming to be
> compliant with the architecture, and defines ATTR_TYPE_OVR as a new
> feature discovered from IDR1.
> This also required to propagate the SMMU through some functions args.
> 
> There is no need to add similar condition for the newly introduced function
> arm_smmu_get_ste_used() as the values of the STE are the same before and
> after any transition, so this will not trigger any change. (we already
> do the same for the VMID).
> 
> Although this is a misconfiguration from the driver, this has been there
> for a long time, so probably no HW running Linux is affected by it.
> 
> Reported-by: Will Deacon <will at kernel.org>
> Closes: https://lore.kernel.org/all/20240215134952.GA690@willie-the-truck/
> Signed-off-by: Mostafa Saleh <smostafa at google.com>
> ---
>  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 35 ++++++++++++++-------
>  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h |  2 ++
>  2 files changed, 25 insertions(+), 12 deletions(-)

Reviewed-by: Jason Gunthorpe <jgg at nvidia.com>

Thanks,
Jason