[PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port

[AngeloGioacchino Del Regno]

Il 13/03/24 23:05, Daniel Golle ha scritto:
> Due to what seems to be an undocumented oddity in MediaTek's MT7988
> SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
> CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.
> 
> This currently leads to PCIe port 2 not working in Linux.
> 
> Reflect the apparent relationship in the clk driver to make sure PCIe
> port 2 of the MT7988 SoC works.
> 
> Fixes: 4b4719437d85f ("clk: mediatek: add drivers for MT7988 SoC")
> Suggested-by: Sam Shih <sam.shih at mediatek.com>
> Signed-off-by: Daniel Golle <daniel at makrotopia.org>

That's funny. Anyway:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

> ---
>   drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c
> index 449041f8abbc9..c8c023afe3e5a 100644
> --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
> +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
> @@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[] = {
>   	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
>   		    "csw_infra_f26m_sel", 8),
>   	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
> -		    "csw_infra_f26m_sel", 9),
> +		    "infra_pcie_peri_ck_26m_ck_p3", 9),
>   	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
>   		    "csw_infra_f26m_sel", 10),
>   	/* INFRA1 */