[PATCH v2 2/3] mips: dts: ralink: mt7621: reorder serial0 properties

[Justin Swartz]

Reorder serial0 properties according to the guidelines laid
out in Documentation/devicetree/bindings/dts-coding-style.rst

Signed-off-by: Justin Swartz <justin.swartz at risingedge.co.za>
---
 arch/mips/boot/dts/ralink/mt7621.dtsi | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index dca415fdd..3ad4e2343 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -114,16 +114,12 @@ memc: memory-controller at 5000 {
 		serial0: serial at c00 {
 			compatible = "ns16550a";
 			reg = <0xc00 0x100>;
-
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			clocks = <&sysc MT7621_CLK_UART1>;
-
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
-
-			reg-shift = <2>;
-			reg-io-width = <4>;
 			no-loopback-test;
-
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart1_pins>;
 		};
--