[PATCH v4 4/4] arm64: dts: imx8qxp: add asrc[0, 1], esai0, spdif[0, 1] and sai[4, 5]
Alexander Stein
alexander.stein at ew.tq-group.com
Wed Mar 6 23:22:25 PST 2024
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Hi Frank,
Am Mittwoch, 6. März 2024, 16:19:18 CET schrieb Frank Li:
> On Wed, Mar 06, 2024 at 08:20:00AM +0100, Alexander Stein wrote:
> > Hi Frank,
> >
> > thanks for the patch.
> >
> > Am Dienstag, 5. März 2024, 18:33:05 CET schrieb Frank Li:
> > > Add asrc[0,1], esai0, spdif[0,1], sai[4,5] and related lpcg node for
> > > imx8 audio subsystem.
> > >
> > > Signed-off-by: Frank Li <Frank.Li at nxp.com>
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 304 +++++++++++++++++++++++
> > > 1 file changed, 304 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> > > index 07afeb78ed564..78305559f15c9 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> > > @@ -6,6 +6,7 @@
> > >
> > > #include <dt-bindings/clock/imx8-clock.h>
> > > #include <dt-bindings/clock/imx8-lpcg.h>
> > > +#include <dt-bindings/dma/fsl-edma.h>
> > > #include <dt-bindings/firmware/imx/rsrc.h>
> > >
> > > audio_ipg_clk: clock-audio-ipg {
> > > @@ -481,4 +482,307 @@ acm: acm at 59e00000 {
> > > "sai3_rx_bclk",
> > > "sai4_rx_bclk";
> > > };
> > > +
> > > + asrc0: asrc at 59000000 {
> >
> > Please insert nodes sorted by address. ASRC0 is the very first node.
> >
> > > + compatible = "fsl,imx8qm-asrc";
> > > + reg = <0x59000000 0x10000>;
> > > + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&asrc0_lpcg 0>,
> > > + <&asrc0_lpcg 0>,
> > > + <&aud_pll_div0_lpcg 0>,
> > > + <&aud_pll_div1_lpcg 0>,
> > > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
> > > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>;
> > > + clock-names = "mem", "ipg",
> > > + "asrck_0", "asrck_1", "asrck_2", "asrck_3",
> > > + "asrck_4", "asrck_5", "asrck_6", "asrck_7",
> > > + "asrck_8", "asrck_9", "asrck_a", "asrck_b",
> > > + "asrck_c", "asrck_d", "asrck_e", "asrck_f",
> > > + "spba";
> > > + dmas = <&edma0 0 0 0>,
> > > + <&edma0 1 0 0>,
> > > + <&edma0 2 0 0>,
> > > + <&edma0 3 0 FSL_EDMA_RX>,
> > > + <&edma0 4 0 FSL_EDMA_RX>,
> > > + <&edma0 5 0 FSL_EDMA_RX>;
> > > + /* tx* is output channel of asrc, it is rx channel for eDMA */
> > > + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
> > > + fsl,asrc-rate = <8000>;
> > > + fsl,asrc-width = <16>;
> > > + fsl,asrc-clk-map = <0>;
> > > + power-domains = <&pd IMX_SC_R_ASRC_0>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + esai0: esai at 59010000 {
> > > + compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai";
> > > + reg = <0x59010000 0x10000>;
> > > + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&clk_dummy>;
> > > + clock-names = "core", "extal", "fsys", "spba";
> > > + dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>;
> > > + dma-names = "rx", "tx";
> > > + power-domains = <&pd IMX_SC_R_ESAI_0>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + spdif0: spdif at 59020000 {
> > > + compatible = "fsl,imx8qm-spdif";
> > > + reg = <0x59020000 0x10000>;
> > > + interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
> > > + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
> > > + clocks = <&spdif0_lpcg 1>, /* core */
> > > + <&clk_dummy>, /* rxtx0 */
> > > + <&spdif0_lpcg 0>, /* rxtx1 */
> > > + <&clk_dummy>, /* rxtx2 */
> > > + <&clk_dummy>, /* rxtx3 */
> > > + <&clk_dummy>, /* rxtx4 */
> > > + <&audio_ipg_clk>, /* rxtx5 */
> > > + <&clk_dummy>, /* rxtx6 */
> > > + <&clk_dummy>, /* rxtx7 */
> > > + <&clk_dummy>; /* spba */
> > > + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
> > > + "rxtx5", "rxtx6", "rxtx7", "spba";
> > > + dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
> > > + <&edma0 9 0 FSL_EDMA_MULTI_FIFO>;
> > > + dma-names = "rx", "tx";
> > > + power-domains = <&pd IMX_SC_R_SPDIF_0>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + spdif1: spdif at 59030000 {
> >
> > That's imx8qm only, no?
>
> I am not sure what means. why do you think it is imx8qm only? It is for
> imx8qm, imx8qxp, imx8dxl.
According to Table- 2-6 (Audio DMA memory Map) in i.MX8X RM Rev. 0 05/2020,
the lasted one available on the webpage, address 0x59030000 is reserved.
I read that as there is no periphery available. This matches the feature list
in 1.1.2 Features, where "1x SPDIF" is stated.
So spdif1 is only for imx8qm (no idea about imx8dxl though) and should be
listed in a file called imx8qm-ss-audio.dtsi which is only included in
imx8qm.dtsi.
Thanks and best regards
Alexander
>
> Frank
>
> >
> > > + compatible = "fsl,imx8qm-spdif";
> > > + reg = <0x59030000 0x10000>;
> > > + interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */
> > > + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */
> > > + clocks = <&spdif1_lpcg 1>, /* core */
> > > + <&clk_dummy>, /* rxtx0 */
> > > + <&spdif1_lpcg 0>, /* rxtx1 */
> > > + <&clk_dummy>, /* rxtx2 */
> > > + <&clk_dummy>, /* rxtx3 */
> > > + <&clk_dummy>, /* rxtx4 */
> > > + <&audio_ipg_clk>, /* rxtx5 */
> > > + <&clk_dummy>, /* rxtx6 */
> > > + <&clk_dummy>, /* rxtx7 */
> > > + <&clk_dummy>; /* spba */
> > > + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
> > > + "rxtx5", "rxtx6", "rxtx7", "spba";
> > > + dmas = <&edma0 10 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
> > > + <&edma0 11 0 FSL_EDMA_MULTI_FIFO>;
> > > + dma-names = "rx", "tx";
> > > + power-domains = <&pd IMX_SC_R_SPDIF_1>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + asrc1: asrc at 59800000 {
> >
> > Insert this between dsp and edma1, sorted by address.
> >
> > > + compatible = "fsl,imx8qm-asrc";
> > > + reg = <0x59800000 0x10000>;
> > > + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&asrc1_lpcg 0>,
> > > + <&asrc1_lpcg 0>,
> > > + <&aud_pll_div0_lpcg 0>,
> > > + <&aud_pll_div1_lpcg 0>,
> > > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
> > > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>;
> > > + clock-names = "mem", "ipg",
> > > + "asrck_0", "asrck_1", "asrck_2", "asrck_3",
> > > + "asrck_4", "asrck_5", "asrck_6", "asrck_7",
> > > + "asrck_8", "asrck_9", "asrck_a", "asrck_b",
> > > + "asrck_c", "asrck_d", "asrck_e", "asrck_f",
> > > + "spba";
> > > + dmas = <&edma1 0 0 0>,
> > > + <&edma1 1 0 0>,
> > > + <&edma1 2 0 0>,
> > > + <&edma1 3 0 FSL_EDMA_RX>,
> > > + <&edma1 4 0 FSL_EDMA_RX>,
> > > + <&edma1 5 0 FSL_EDMA_RX>;
> > > + /* tx* is output channel of asrc, it is rx channel for eDMA */
> > > + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
> > > + fsl,asrc-rate = <8000>;
> > > + fsl,asrc-width = <16>;
> > > + fsl,asrc-clk-map = <1>;
> > > + power-domains = <&pd IMX_SC_R_ASRC_1>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + sai4: sai at 59820000 {
> > > + compatible = "fsl,imx8qm-sai";
> > > + reg = <0x59820000 0x10000>;
> > > + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&sai4_lpcg 1>,
> > > + <&clk_dummy>,
> > > + <&sai4_lpcg 0>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>;
> > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
> > > + dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>;
> > > + dma-names = "rx", "tx";
> > > + power-domains = <&pd IMX_SC_R_SAI_4>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + sai5: sai at 59830000 {
> > > + compatible = "fsl,imx8qm-sai";
> > > + reg = <0x59830000 0x10000>;
> > > + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&sai5_lpcg 1>,
> > > + <&clk_dummy>,
> > > + <&sai5_lpcg 0>,
> > > + <&clk_dummy>,
> > > + <&clk_dummy>;
> > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
> > > + dmas = <&edma1 10 0 0>;
> > > + dma-names = "tx";
> > > + power-domains = <&pd IMX_SC_R_SAI_5>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + amix: amix at 59840000 {
> > > + compatible = "fsl,imx8qm-audmix";
> > > + reg = <0x59840000 0x10000>;
> > > + clocks = <&amix_lpcg 0>;
> > > + clock-names = "ipg";
> > > + power-domains = <&pd IMX_SC_R_AMIX>;
> > > + dais = <&sai4>, <&sai5>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + mqs: mqs at 59850000 {
> > > + compatible = "fsl,imx8qm-mqs";
> > > + reg = <0x59850000 0x10000>;
> > > + clocks = <&mqs0_lpcg 0>,
> > > + <&mqs0_lpcg 1>;
> > > + clock-names = "mclk", "core";
> > > + power-domains = <&pd IMX_SC_R_MQS_0>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + asrc0_lpcg: clock-controller at 59400000 {
> >
> > Please insert he lpcg nodes according to their address.
> >
> > > + compatible = "fsl,imx8qxp-lpcg";
> > > + reg = <0x59400000 0x10000>;
> > > + #clock-cells = <1>;
> > > + clocks = <&audio_ipg_clk>;
> > > + clock-indices = <IMX_LPCG_CLK_4>;
> > > + clock-output-names = "asrc0_lpcg_ipg_clk";
> > > + power-domains = <&pd IMX_SC_R_ASRC_0>;
> > > + };
> > > +
> > > + esai0_lpcg: clock-controller at 59410000 {
> > > + compatible = "fsl,imx8qxp-lpcg";
> > > + reg = <0x59410000 0x10000>;
> > > + #clock-cells = <1>;
> > > + clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
> > > + <&audio_ipg_clk>;
> > > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > > + clock-output-names = "esai0_lpcg_extal_clk",
> > > + "esai0_lpcg_ipg_clk";
> > > + power-domains = <&pd IMX_SC_R_ESAI_0>;
> > > + };
> > > +
> > > + spdif0_lpcg: clock-controller at 59420000 {
> > > + compatible = "fsl,imx8qxp-lpcg";
> > > + reg = <0x59420000 0x10000>;
> > > + #clock-cells = <1>;
> > > + clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>,
> > > + <&audio_ipg_clk>;
> > > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > > + clock-output-names = "spdif0_lpcg_tx_clk",
> > > + "spdif0_lpcg_gclkw";
> > > + power-domains = <&pd IMX_SC_R_SPDIF_0>;
> > > + };
> > > +
> > > + spdif1_lpcg: clock-controller at 59430000 {
> >
> > That's imx8qm only as well, no?
> >
> > Thanks and best regards,
> > Alexander
> >
> > > + compatible = "fsl,imx8qxp-lpcg";
> > > + reg = <0x59430000 0x10000>;
> > > + #clock-cells = <1>;
> > > + clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>,
> > > + <&audio_ipg_clk>;
> > > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > > + clock-output-names = "spdif1_lpcg_tx_clk",
> > > + "spdif1_lpcg_gclkw";
> > > + power-domains = <&pd IMX_SC_R_SPDIF_1>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + asrc1_lpcg: clock-controller at 59c00000 {
> > > + compatible = "fsl,imx8qxp-lpcg";
> > > + reg = <0x59c00000 0x10000>;
> > > + #clock-cells = <1>;
> > > + clocks = <&audio_ipg_clk>;
> > > + clock-indices = <IMX_LPCG_CLK_4>;
> > > + clock-output-names = "asrc1_lpcg_ipg_clk";
> > > + power-domains = <&pd IMX_SC_R_ASRC_1>;
> > > + };
> > > +
> > > + sai4_lpcg: clock-controller at 59c20000 {
> > > + compatible = "fsl,imx8qxp-lpcg";
> > > + reg = <0x59c20000 0x10000>;
> > > + #clock-cells = <1>;
> > > + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
> > > + <&audio_ipg_clk>;
> > > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > > + clock-output-names = "sai4_lpcg_mclk",
> > > + "sai4_lpcg_ipg_clk";
> > > + power-domains = <&pd IMX_SC_R_SAI_4>;
> > > + };
> > > +
> > > + sai5_lpcg: clock-controller at 59c30000 {
> > > + compatible = "fsl,imx8qxp-lpcg";
> > > + reg = <0x59c30000 0x10000>;
> > > + #clock-cells = <1>;
> > > + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
> > > + <&audio_ipg_clk>;
> > > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > > + clock-output-names = "sai5_lpcg_mclk",
> > > + "sai5_lpcg_ipg_clk";
> > > + power-domains = <&pd IMX_SC_R_SAI_5>;
> > > + };
> > > +
> > > + amix_lpcg: clock-controller at 59c40000 {
> > > + compatible = "fsl,imx8qxp-lpcg";
> > > + reg = <0x59c40000 0x10000>;
> > > + #clock-cells = <1>;
> > > + clocks = <&audio_ipg_clk>;
> > > + clock-indices = <IMX_LPCG_CLK_0>;
> > > + clock-output-names = "amix_lpcg_ipg_clk";
> > > + power-domains = <&pd IMX_SC_R_AMIX>;
> > > + };
> > > +
> > > + mqs0_lpcg: clock-controller at 59c50000 {
> > > + compatible = "fsl,imx8qxp-lpcg";
> > > + reg = <0x59c50000 0x10000>;
> > > + #clock-cells = <1>;
> > > + clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>,
> > > + <&audio_ipg_clk>;
> > > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > > + clock-output-names = "mqs0_lpcg_mclk",
> > > + "mqs0_lpcg_ipg_clk";
> > > + power-domains = <&pd IMX_SC_R_MQS_0>;
> > > + };
> > > };
> > >
> > >
> >
> >
>
>
--
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Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
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