mx93: No cache hierachy definitions for ARM cores

[Peng Fan]

> Subject: Re: mx93: No cache hierachy definitions for ARM cores
> 
> Am 24.07.24 um 16:34 schrieb Sudeep Holla:
> > On Wed, Jul 24, 2024 at 11:48:13AM +0200, Stefan Wahren wrote:
> >> Hi Frank,
> >>
> >> Am 19.07.24 um 16:52 schrieb Frank Li:
> >>> On Thu, Jul 18, 2024 at 11:38:20PM -0300, Fabio Estevam wrote:
> >>>> On Wed, Jul 17, 2024 at 2:49 PM Stefan Wahren
> <wahrenst at gmx.net> wrote:
> >>>>> Hi,
> >>>>> today i noticed that imx93.dtsi lacks the cache definitions for
> >>>>> the
> >>>>> Cortex-A55 cores:
> >>>>>
> >>>>> cacheinfo: Unable to detect cache hierarchy for CPU 0
> >>>>>
> >>>>> Maybe someone with more insight can add this to the
> imx93.dtsi file.
> >>>> Frank, can you help?
> >>> Peng:
> >>> 	Some informatin missed at public RM. Can you help this? I
> found it
> >>> also missed in internal tree.
> >> does the official ARM documentation [1] provide the missing
> information?

ARM provides several cache options for vendor to choose. I will give
a look and post a patch for i.MX93 A55 cache info.

Regards,
Peng.

> >>
> >> [1] -
> >> rved=0
> > I assume you meant [2] instead of [1], as Cortex A55 and M55 are
> different.
> Sorry, you are absolutely right.
> >
> > --
> > Regards,
> > Sudeep
> >
> > [2]
> >
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> deve
> >
> loper.arm.com%2Fdocumentation%2F100442%2F0200%2F&data=05%
> 7C02%7Cpeng.f
> >
> an%40nxp.com%7C4bbe72bc89434c01562208dcabf90c5f%7C686ea1
> d3bc2b4c6fa92c
> >
> d99c5c301635%7C0%7C0%7C638574333341297713%7CUnknown%7
> CTWFpbGZsb3d8eyJW
> >
> IjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> 3D%7C0%7C%
> >
> 7C%7C&sdata=rXF3vAX9pKXv%2FAoKmCmb5K1XPDPvu2e3aAq4jzR6F
> QE%3D&reserved=
> > 0