[PATCH v3 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support

[Jianjun Wang (王建军)]

On Sat, 2024-06-29 at 15:51 +0200, Lorenzo Bianconi wrote:
>  	 
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>  Introduce support for Airoha EN7581 PCIe controller to mediatek-gen3
> PCIe controller driver.
> 
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno at collabora.com>
> Tested-by: Zhengping Zhang <zhengping.zhang at airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
> ---
>  drivers/pci/controller/Kconfig              |   2 +-
>  drivers/pci/controller/pcie-mediatek-gen3.c | 108
> +++++++++++++++++++-
>  2 files changed, 108 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/Kconfig
> b/drivers/pci/controller/Kconfig
> index e534c02ee34f..3bd6c9430010 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -196,7 +196,7 @@ config PCIE_MEDIATEK
>  
>  config PCIE_MEDIATEK_GEN3
>  	tristate "MediaTek Gen3 PCIe controller"
> -	depends on ARCH_MEDIATEK || COMPILE_TEST
> +	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
>  	depends on PCI_MSI
>  	help
>  	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 438a5222d986..f3f76d1bfd4c 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -7,6 +7,7 @@
>   */
>  
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
>  #include <linux/delay.h>
>  #include <linux/iopoll.h>
>  #include <linux/irq.h>
> @@ -15,6 +16,8 @@
>  #include <linux/kernel.h>
>  #include <linux/module.h>
>  #include <linux/msi.h>
> +#include <linux/of_device.h>
> +#include <linux/of_pci.h>
>  #include <linux/pci.h>
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
> @@ -29,6 +32,12 @@
>  #define PCI_CLASS(class)		(class << 8)
>  #define PCIE_RC_MODE			BIT(0)
>  
> +#define PCIE_EQ_PRESET_01_REG		0x100
> +#define PCIE_VAL_LN0_DOWNSTREAM		GENMASK(6, 0)
> +#define PCIE_VAL_LN0_UPSTREAM		GENMASK(14, 8)
> +#define PCIE_VAL_LN1_DOWNSTREAM		GENMASK(22, 16)
> +#define PCIE_VAL_LN1_UPSTREAM		GENMASK(30, 24)
> +
>  #define PCIE_CFGNUM_REG			0x140
>  #define PCIE_CFG_DEVFN(devfn)		((devfn) & GENMASK(7,
> 0))
>  #define PCIE_CFG_BUS(bus)		(((bus) << 8) & GENMASK(15, 8))
> @@ -68,6 +77,14 @@
>  #define PCIE_MSI_SET_ENABLE_REG		0x190
>  #define PCIE_MSI_SET_ENABLE		GENMASK(PCIE_MSI_SET_NUM - 1,
> 0)
>  
> +#define PCIE_PIPE4_PIE8_REG		0x338
> +#define PCIE_K_FINETUNE_MAX		GENMASK(5, 0)
> +#define PCIE_K_FINETUNE_ERR		GENMASK(7, 6)
> +#define PCIE_K_PRESET_TO_USE		GENMASK(18, 8)
> +#define PCIE_K_PHYPARAM_QUERY		BIT(19)
> +#define PCIE_K_QUERY_TIMEOUT		BIT(20)
> +#define PCIE_K_PRESET_TO_USE_16G	GENMASK(31, 21)
> +
>  #define PCIE_MSI_SET_BASE_REG		0xc00
>  #define PCIE_MSI_SET_OFFSET		0x10
>  #define PCIE_MSI_SET_STATUS_OFFSET	0x04
> @@ -100,7 +117,13 @@
>  #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
>  #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
>  
> -#define MAX_NUM_PHY_RESETS		1
> +#define MAX_NUM_PHY_RESETS		3
> +
> +/* EN7581 */
> +/* PCIe-PHY initialization delay in ms */
> +#define PHY_INIT_TIME_MS		30

Since we have already moved the PHY related settings to the PHY driver,
can we also move this init time to the PHY driver?

Thanks.

> +/* PCIe reset line delay in ms */
> +#define PCIE_RESET_TIME_MS		100
>  
>  struct mtk_gen3_pcie;
>