[PATCH v2 10/28] spi: s3c64xx: use full mask for {RX, TX}_FIFO_LVL

[Mark Brown]

On Thu, Jan 25, 2024 at 02:03:15PM -0600, Sam Protsenko wrote:
> On Thu, Jan 25, 2024 at 8:50 AM Tudor Ambarus <tudor.ambarus at linaro.org> wrote:

> > +#define S3C64XX_SPI_ST_RX_FIFO_LVL             GENMASK(23, 15)

> What about s3c* architectures, where RX_LVL starts with bit #13, as
> can be seen from .rx_lvl_offset values in corresponding port_configs?
> Wouldn't this change break those?

I should point out that I have a s3c6410 board I care about.
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