[PATCH v2] net: stmmac: Wait a bit for the reset to take effect

[Bernd Edlinger]

On 1/16/24 23:35, Andrew Lunn wrote:
> On Mon, Jan 15, 2024 at 08:21:42PM +0100, Bernd Edlinger wrote:
>> otherwise the synopsys_id value may be read out wrong,
>> because the GMAC_VERSION register might still be in reset
>> state, for at least 1 us after the reset is de-asserted.
>>
>> Add a wait for 10 us before continuing to be on the safe side.
>>
>>> From what have you got that delay value?
>>
>> Just try and error, with very old linux versions and old gcc versions
>> the synopsys_id was read out correctly most of the time (but not always),
>> with recent linux versions and recnet gcc versions it was read out
>> wrongly most of the time, but again not always.
>> I don't have access to the VHDL code in question, so I cannot
>> tell why it takes so long to get the correct values, I also do not
>> have more than a few hardware samples, so I cannot tell how long
>> this timeout must be in worst case.
>> Experimentally I can tell that the register is read several times
>> as zero immediately after the reset is de-asserted
> 
> Is zero a valid synopsys_id? If its not, maybe do the wait conditional
> on the first read returning 0?
> 

I don't know at all.  And actually, I am more concerned that other registers
might be unreliable within the first microsecond after reset is de-asserted.

As I mentioned earlier the VHDL source code is obfuscated and I cannot
tell anything about it, maybe people from synopsys can shed some light
on the issue.


Thanks
Bernd.