[RFC 2/9] arm64: dts: qcom: qrb5165-rb5: describe the WLAN module of QCA6390

[Bartosz Golaszewski]

On Thu, Jan 4, 2024 at 2:44 PM Dmitry Baryshkov
<dmitry.baryshkov at linaro.org> wrote:
>
> On Thu, 4 Jan 2024 at 15:03, Bartosz Golaszewski <brgl at bgdev.pl> wrote:
> >
> > From: Bartosz Golaszewski <bartosz.golaszewski at linaro.org>
> >
> > Describe the ath11k WLAN on-board the QCA6390 module. Include the
> > relevant regulators and the enable GPIO.
> >
> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski at linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 24 ++++++++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
> > index cd0db4f31d4a..721f86af952b 100644
> > --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
> > +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
> > @@ -734,6 +734,22 @@ &pcie0_phy {
> >         vdda-pll-supply = <&vreg_l9a_1p2>;
> >  };
> >
> > +&pcieport0 {
> > +       wifi at 0 {
> > +               compatible = "pci17cb,1101";
> > +               reg = <0x10000 0x0 0x0 0x0 0x0>;
> > +
> > +               pinctrl-names = "default";
> > +               pinctrl-0 = <&wlan_en_state>;
> > +
> > +               enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
> > +
> > +               vddpmu-supply = <&vreg_s2f_0p95>;
> > +               vddpcie1-supply = <&vreg_s8c_1p3>;
> > +               vddpcie2-supply = <&vreg_s5a_1p9>;
>
> If I remember correctly, qca6390 has at least 8 power supplies AON,
> PMU, 3xRFA, 2xPCIe and VDDIO.
>
> Moreover, these bindings do not solve another problem: the PMU is
> shared between WiFi and BT parts. For the next gen (WCN6855) this
> becomes even more important, see the code in msm-5.10 which makes sure
> that there is a proper time between one of the units going down and
> another one being powered on.
>

Unified, shared power sequencing for this type of loosely coupled MFD
devices is something I have in mind and that will be orthogonal to
this. It will come on top of the PCIe power sequencing driver. I
wanted to address a simpler issue first.

Bartosz

> > +       };
> > +};
> > +
> >  &pcie1 {
> >         status = "okay";
> >  };
> > @@ -1303,6 +1319,14 @@ sdc2_card_det_n: sd-card-det-n-state {
> >                 function = "gpio";
> >                 bias-pull-up;
> >         };
> > +
> > +       wlan_en_state: wlan-default-state {
> > +               pins = "gpio20";
> > +               function = "gpio";
> > +               drive-strength = <16>;
> > +               output-low;
> > +               bias-pull-up;
> > +       };
> >  };
> >
> >  &uart6 {
> > --
> > 2.40.1
> >
> >
>
>
> --
> With best wishes
> Dmitry