[PATCH v5 1/7] dt-bindings: iommu: Add Qualcomm TBU bindings

[Georgi Djakov]

Hi Krzysztof,

On 29.02.24 19:53, Krzysztof Kozlowski wrote:
> On 26/02/2024 18:22, Georgi Djakov wrote:
>> The "apps_smmu" on the Qualcomm sdm845 platform is an implementation
>> of the SMMU-500, that consists of a single TCU (Translation Control
>> Unit) and multiple TBUs (Translation Buffer Units). These TBUs have
>> hardware debugging features that are specific and only present on
>> Qualcomm hardware. Represent them as independent DT nodes. List all
>> the resources that are needed to operate them (such as registers,
>> clocks, power domains and interconnects).
>>
>> Signed-off-by: Georgi Djakov <quic_c_gdjako at quicinc.com>
>> ---
>>   .../devicetree/bindings/iommu/qcom,tbu.yaml   | 65 +++++++++++++++++++
>>   1 file changed, 65 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/iommu/qcom,tbu.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/qcom,tbu.yaml b/Documentation/devicetree/bindings/iommu/qcom,tbu.yaml
>> new file mode 100644
>> index 000000000000..6841ca9af21f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iommu/qcom,tbu.yaml
>> @@ -0,0 +1,65 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/iommu/qcom,tbu.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm TBU (Translation Buffer Unit)
>> +
>> +maintainers:
>> +  - Georgi Djakov <quic_c_gdjako at quicinc.com>
>> +
>> +description:
>> +  The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains
>> +  a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides
>> +  debug features to trace and trigger debug transactions. There are multiple TBU
>> +  instances with each client core.
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,qsmmuv500-tbu
> 
> Why we don't have SoC specific compatibles? If that's for SDM845, then
> it should be qcom,sdm845-tbu or qcom,sdm845-qsmmuv500-tbu
> 

Because they should be all compatible (as registers). Adding a SoC compatible
might get overly-specific, but i can also see the benefits in that, so ok will
do it!

> 
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    maxItems: 1
>> +
>> +  interconnects:
>> +    maxItems: 1
>> +
>> +  power-domains:
>> +    maxItems: 1
>> +
>> +  qcom,stream-id-range:
>> +    description: Phandle of a SMMU device and Stream ID range (address and size) that is assigned by the TBU
> 
> Please wrap it according to coding style, so 80.
> 

Sure, thanks!

>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +      - items:
>> +          - description: phandle of a smmu node
>> +          - description: stream id base address
>> +          - description: stream id size
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - qcom,stream-id-range
>> +
>> +unevaluatedProperties: false
> 
> This should be additionalProperties: false
> 

Ok right, thanks for taking a look!

BR,
Georgi