[PATCH v3 1/4] arm64: dts: imx8mp-phyboard-pollux: Add and update rtc devicetree node
Yashwanth Varakala
y.varakala at phytec.de
Fri Feb 23 09:22:08 PST 2024
The interrupt of the RTC is connected on the carrier board
phyBOARD-i.MX8MP-Pollux.
RTC trickle-charger devicetree property is dependent on the
phyboard-pollux design.
Signed-off-by: Yashwanth Varakala <y.varakala at phytec.de>
---
Changes in v2:
-Corrected the commit message.
.../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 15 +++++++++++++++
.../boot/dts/freescale/imx8mp-phycore-som.dtsi | 1 -
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 9e8afceba65e..894905fb42b0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -191,6 +191,15 @@ ldb_lvds_ch1: endpoint {
};
};
+&rv3028 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ trickle-resistor-ohms = <3000>;
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -369,6 +378,12 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
+ pinctrl_rtc: rtcgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index c976c3b6cbc6..e6ffa6a6b68b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -175,7 +175,6 @@ eeprom at 51 {
rv3028: rtc at 52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
- trickle-resistor-ohms = <3000>;
};
};
--
2.34.1
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