[PATCH v5 1/7] soc: sunxi: sram: export register 0 for THS on H616

[Jernej Škrabec]

Dne četrtek, 22. februar 2024 ob 19:44:12 CET je Daniel Lezcano napisal(a):
> On 22/02/2024 19:26, Jernej Škrabec wrote:
> > Dne ponedeljek, 19. februar 2024 ob 16:36:33 CET je Andre Przywara napisal(a):
> >> The Allwinner H616 SoC contains a mysterious bit at register offset 0x0
> >> in the SRAM control block. If bit 16 is set (the reset value), the
> >> temperature readings of the THS are way off, leading to reports about
> >> 200C, at normal ambient temperatures. Clearing this bits brings the
> >> reported values down to the expected values.
> >> The BSP code clears this bit in firmware (U-Boot), and has an explicit
> >> comment about this, but offers no real explanation.
> >>
> >> Experiments in U-Boot show that register 0x0 has no effect on the SRAM C
> >> visibility: all tested bit settings still allow full read and write
> >> access by the CPU to the whole of SRAM C. Only bit 24 of the register at
> >> offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling
> >> the THS switch functionality as an SRAM region would not reflect reality.
> >>
> >> Since we should not rely on firmware settings, allow other code (the THS
> >> driver) to access this register, by exporting it through the already
> >> existing regmap. This mimics what we already do for the LDO control and
> >> the EMAC register.
> >>
> >> To avoid concurrent accesses to the same register at the same time, by
> >> the SRAM switch code and the regmap code, use the same lock to protect
> >> the access. The regmap subsystem allows to use an existing lock, so we
> >> just need to hook in there.
> >>
> >> Signed-off-by: Andre Przywara <andre.przywara at arm.com>
> > 
> > Reviewed-by: Jernej Skrabec <jernej.skrabec at gmail.com>
> > 
> > I guess this one goes through sunxi tree, right?
> 
> I'll pick this patch along with the patch 2-6, so through the thermal 
> tree. The patch 7/7 will go indeed via the sunxi tree

Ok.

Best regards,
Jernej