[PATCH v2 2/4] arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board

[Lorenzo Bianconi]

> On 21/02/2024 01:04, Lorenzo Bianconi wrote:
> > From: Daniel Danzberger <dd at embedd.com>
> > 
> > Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation
> > Board's dts file, as well as the required Makefiles.
> > 
> > Signed-off-by: Daniel Danzberger <dd at embedd.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo at kernel.org>
> > ---
> >  arch/arm64/boot/dts/Makefile              |   1 +
> >  arch/arm64/boot/dts/airoha/Makefile       |   2 +
> >  arch/arm64/boot/dts/airoha/en7581-evb.dts |  27 +++++
> >  arch/arm64/boot/dts/airoha/en7581.dtsi    | 137 ++++++++++++++++++++++
> >  4 files changed, 167 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/airoha/Makefile
> >  create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts
> >  create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> > index 30dd6347a929..21cd3a87f385 100644
> > --- a/arch/arm64/boot/dts/Makefile
> > +++ b/arch/arm64/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >  subdir-y += actions
> > +subdir-y += airoha
> >  subdir-y += allwinner
> >  subdir-y += altera
> >  subdir-y += amazon
> > diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile
> > new file mode 100644
> > index 000000000000..ebea112ce1d7
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/airoha/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb
> > diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts
> > new file mode 100644
> > index 000000000000..4eaa8ac431c3
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts
> > @@ -0,0 +1,27 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/dts-v1/;
> > +
> > +/* Bootloader installs ATF here */
> > +/memreserve/ 0x80000000 0x200000;
> > +
> > +#include "en7581.dtsi"
> > +
> > +/ {
> > +	model = "Airoha EN7581 Evaluation Board";
> > +	compatible = "airoha,en7581-evb", "airoha,en7581";
> > +
> > +	aliases {
> > +		serial0 = &uart1;
> > +	};
> > +
> > +	chosen {
> > +		bootargs = "console=ttyS0,115200 earlycon";
> 
> You have console below. You don't need earlycon for mainline, broad
> usage, because it is purely debugging part, so drop entire bootargs.

ack, I will fix it in v3.

> 
> > +		stdout-path = "serial0:115200n8";
> > +		linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
> > +	};
> > +
> > +	memory at 80000000 {
> > +		device_type = "memory";
> > +		reg = <0x0 0x80000000 0x2 0x00000000>;
> > +	};
> > +};
> > diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> > new file mode 100644
> > index 000000000000..7a3c0a45c03f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
> > @@ -0,0 +1,137 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	interrupt-parent = <&gic>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	reserved-memory {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		npu_binary at 84000000 {
> 
> No underscores in nodenames.
> ...
> 

ack, I will fix it in v3.

> > +
> > +		L2_0: l2-cache0 {
> 
> Nodename: l2-cache
> 

ack, I will fix it in v3.

> > +			compatible = "cache";
> > +			cache-level = <2>;
> > +			cache-unified;
> > +		};
> > +	};
> > +
> > +	gic: interrupt-controller at 9000000 {
> 
> Why this is outside of SoC? Where is your SoC node BTW?

ack, I will fix it in v3.

> 
> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check W=1` (see
> Documentation/devicetree/bindings/writing-schema.rst or
> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
> for instructions).
> 
> > +		compatible = "arm,gic-v3";
> > +		interrupt-controller;
> > +		#interrupt-cells = <3>;
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		reg = <0x0 0x09000000 0x0 0x20000>,
> > +		      <0x0 0x09080000 0x0 0x80000>,
> > +		      <0x0 0x09400000 0x0 0x2000>,
> > +		      <0x0 0x09500000 0x0 0x2000>,
> > +		      <0x0 0x09600000 0x0 0x20000>;
> > +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > +	};
> > +
> > +	uart1: serial at 1fbf0000 {
> 
> This cannot be outside of SoC.

ack, I will fix it in v3.

> 
> > +		compatible = "ns16550";
> > +		reg = <0x0 0x1fbf0000 0x0 0x30>;
> > +		reg-io-width = <4>;
> > +		reg-shift = <2>;
> > +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > +		clock-frequency = <1843200>;
> > +		status = "okay";
> 
> Drop

ack, I will fix it in v3.

Regards,
Lorenzo

> 
> 
> Best regards,
> Krzysztof
> 
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