[PATCH] arm64: io: permit offset addressing

[Catalin Marinas]

On Wed, 24 Jan 2024 11:12:59 +0000, Mark Rutland wrote:
> Currently our IO accessors all use register addressing without offsets,
> but we could safely use offset addressing (without writeback) to
> simplify and optimize the generated code.
> 
> To function correctly under a hypervisor which emulates IO accesses, we
> must ensure that any faulting/trapped IO access results in an ESR_ELx
> value with ESR_ELX.ISS.ISV=1 and with the tranfer register described in
> ESR_ELx.ISS.SRT. This means that we can only use loads/stores of a
> single general purpose register (or the zero register), and must avoid
> writeback addressing modes. However, we can use immediate offset
> addressing modes, as these still provide ESR_ELX.ISS.ISV=1 and a valid
> ESR_ELx.ISS.SRT when those accesses fault at Stage-2.
> 
> [...]

Applied to arm64 (for-next/misc), thanks!

[1/1] arm64: io: permit offset addressing
      https://git.kernel.org/arm64/c/d044d6ba6f02

-- 
Catalin