[PATCH] drivers/iommu: Ensure that the queue base address is successfully written during SMMU initialization.

[Daniel Mentz]

On Sat, Feb 17, 2024 at 9:02 PM ni.liqiang <niliqiang.io at gmail.com> wrote:
> If there are no memory barriers, how can we ensure this order?

 The SMMU registers are accessed using Device-nGnRE attributes. It is
my understanding that, for Device-nGnRE, the Arm architecture requires
that writes to the same peripheral arrive at the endpoint in program
order.