[PATCH v3 05/26] KVM: arm64: nv: Add sanitising to VNCR-backed FGT sysregs

[Marc Zyngier]

On Wed, 07 Feb 2024 11:09:08 +0000,
Oliver Upton <oliver.upton at linux.dev> wrote:
> 
> On Wed, Feb 07, 2024 at 10:57:49AM +0000, Oliver Upton wrote:
> > On Mon, Feb 05, 2024 at 10:34:10AM +0000, Marc Zyngier wrote:
> > > Fine Grained Traps are controlled by a whole bunch of features.
> > > Each one of them must be checked and the corresponding masks
> > > computed so that we don't let the guest apply traps it shouldn't
> > > be using.
> > > 
> > > This takes care of HFG[IRW]TR_EL2, HDFG[RW]TR_EL2, and HAFGRTR_EL2.
> > > 
> > > Signed-off-by: Marc Zyngier <maz at kernel.org>
> > > Reviewed-by: Joey Gouly <joey.gouly at arm.com>
> > > ---
> > >  arch/arm64/kvm/nested.c | 128 ++++++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 128 insertions(+)
> > > 
> > > diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
> > > index a8fe0f970e04..31c4ce0439d6 100644
> > > --- a/arch/arm64/kvm/nested.c
> > > +++ b/arch/arm64/kvm/nested.c
> > > @@ -265,6 +265,134 @@ int kvm_init_nv_sysregs(struct kvm *kvm)
> > >  		res1 |= HCR_E2H;
> > >  	set_sysreg_masks(kvm, HCR_EL2, res0, res1);
> > >  
> > > +	/* HFG[RW]TR_EL2 */
> > > +	res0 = res1 = 0;
> > > +	if (!(__vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_ADDRESS) &&
> > > +	      __vcpu_has_feature(&kvm->arch, KVM_ARM_VCPU_PTRAUTH_ADDRESS)))
> > 
> > Same thing here w/ the different flags.

Yup, fixed both occurrences already.

> > 
> > > +	/* HDFG[RW]TR_EL2 */
> > > +	res0 = res1 = 0;
> > > +	if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DoubleLock, IMP))
> > > +		res0 |= HDFGRTR_EL2_OSDLR_EL1;
> > > +	if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP))
> > > +		res0 |= (HDFGRTR_EL2_PMEVCNTRn_EL0 | HDFGRTR_EL2_PMEVTYPERn_EL0 |
> > > +			 HDFGRTR_EL2_PMCCFILTR_EL0 | HDFGRTR_EL2_PMCCNTR_EL0 |
> > > +			 HDFGRTR_EL2_PMCNTEN | HDFGRTR_EL2_PMINTEN |
> > > +			 HDFGRTR_EL2_PMOVS | HDFGRTR_EL2_PMSELR_EL0 |
> > > +			 HDFGRTR_EL2_PMMIR_EL1 | HDFGRTR_EL2_PMUSERENR_EL0 |
> > > +			 HDFGRTR_EL2_PMCEIDn_EL0);
> > 
> > I think you're missing HDFGWTR_EL2_PMSWINC_EL0 and HDFGWTR_EL2_PMCR_EL0
> > here. Silly write-only and read-only registers...
> 
> I can't read. Looks like you're doing this a few lines down.

Yeah, it's a bit tucked away to reuse the previously constructed
masks.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.