[PATCH 2/3] clk: xilinx: vcu: don't set pll_ref as parent of VCU(enc/dec) clocks

[Stephen Boyd]

Quoting Rohit Visavalia (2024-12-26 04:20:22)
> CCF will try to adjust parent clock to set desire clock frequency of
> child clock. So if pll_ref is not a fixed-clock then while setting rate
> of enc/dec clocks pll_ref may get change, which may make VCU malfunction.
> 
> Signed-off-by: Rohit Visavalia <rohit.visavalia at amd.com>
> ---
>  drivers/clk/xilinx/xlnx_vcu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/xilinx/xlnx_vcu.c b/drivers/clk/xilinx/xlnx_vcu.c
> index f294a2398cb4..c3a4df7e325a 100644
> --- a/drivers/clk/xilinx/xlnx_vcu.c
> +++ b/drivers/clk/xilinx/xlnx_vcu.c
> @@ -550,7 +550,7 @@ static int xvcu_register_clock_provider(struct xvcu_device *xvcu)
>                 return PTR_ERR(hw);
>         xvcu->pll_post = hw;
>  
> -       parent_data[0].fw_name = "pll_ref";
> +       parent_data[0].fw_name = "dummy_name";

"dummy_name" isn't part of the binding. It sounds like you want to not
set CLK_SET_RATE_PARENT flag sometimes?

>         parent_data[1].hw = xvcu->pll_post;
>  
>         hws[CLK_XVCU_ENC_CORE] =