[PATCH v3 07/15] drm/bridge: analogix_dp: Add support for phy configuration.

[Diederik de Haas]

On Fri Dec 20, 2024 at 1:13 AM CET, Dmitry Baryshkov wrote:
> On Thu, Dec 19, 2024 at 04:05:56PM +0800, Damon Ding wrote:
> >  void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
> > @@ -546,10 +575,37 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
> >  void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp)
> >  {
> >  	u8 lane;
> > +	int ret;
> >  
> >  	for (lane = 0; lane < dp->link_train.lane_count; lane++)
> >  		writel(dp->link_train.training_lane[lane],
> >  		       dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane);
> > +
> > +	if (dp->phy) {
> > +		union phy_configure_opts phy_cfg = {0};
> > +
> > +		for (lane = 0; lane < dp->link_train.lane_count; lane++) {
> > +			u8 training_lane = dp->link_train.training_lane[lane];
> > +			u8 vs, pe;
> > +
> > +			vs = (training_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>
> > +			     DP_TRAIN_VOLTAGE_SWING_SHIFT;
> > +			pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>
> > +			     DP_TRAIN_PRE_EMPHASIS_SHIFT;
> > +			phy_cfg.dp.voltage[lane] = vs;
> > +			phy_cfg.dp.pre[lane] = pe;
> > +		}
> > +
> > +		phy_cfg.dp.lanes = dp->link_train.lane_count;
> > +		phy_cfg.dp.link_rate =
> > +			drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;
>
> This two should not be necessary, please drop them.

This too or These two (statements)?

> > +		phy_cfg.dp.set_voltages = true;
> > +		ret = phy_configure(dp->phy, &phy_cfg);
> > +		if (ret && ret != -EOPNOTSUPP) {
> > +			dev_err(dp->dev, "%s: phy_configure() failed: %d\n", __func__, ret);
> > +			return;
> > +		}
> > +	}
> >  }
> >  
> >  u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane)
> > -- 
> > 2.34.1
> > 

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