[PATCH 07/15] ARM: zynq: Add ethernet phy reset information to DT(zc702)

[Andrew Lunn]

On Wed, Dec 11, 2024 at 03:04:28PM +0100, Michal Simek wrote:
> Hi Andrew,
> 
> On 12/11/24 14:45, Andrew Lunn wrote:
> > On Wed, Dec 11, 2024 at 01:41:26PM +0100, Michal Simek wrote:
> > > Added phy reset gpio information for gem0.
> > > 
> > > Signed-off-by: Michal Simek <michal.simek at amd.com>
> > > ---
> > > 
> > >   arch/arm/boot/dts/xilinx/zynq-zc702.dts | 2 ++
> > >   1 file changed, 2 insertions(+)
> > > 
> > > diff --git a/arch/arm/boot/dts/xilinx/zynq-zc702.dts b/arch/arm/boot/dts/xilinx/zynq-zc702.dts
> > > index 424e78f6c148..975385f4ac01 100644
> > > --- a/arch/arm/boot/dts/xilinx/zynq-zc702.dts
> > > +++ b/arch/arm/boot/dts/xilinx/zynq-zc702.dts
> > > @@ -79,6 +79,8 @@ &gem0 {
> > >   	phy-handle = <&ethernet_phy>;
> > >   	pinctrl-names = "default";
> > >   	pinctrl-0 = <&pinctrl_gem0_default>;
> > > +	phy-reset-gpio = <&gpio0 11 0>;
> > > +	phy-reset-active-low;
> > 
> > Hi Michal
> > 
> > Could you point me at code which actually implements these two
> > properties.
> 
> I have tracked it down and it was only used from 2016 to 2018 in Xilinx
> downstream Linux repository. After that it was removed.

O.K. So when you ran the DT lint tools to validate these DT changes,
why did it not give errors pointing this out?

I wounder how many other such errors there are in this patchset?

	Andrew