Question about interrupt prioriyt of ARM GICv3/4

[richard clark]

Hi,
Currently seems the GICv3/4 irqchip configures all the interrupts as
the same priority, I am thinking about to minimize the latency of the
interrupt for a particular device, e.g, the arm arch_timer in the RTL
system. The question is,
1. Why don't we provide a /proc or /sys interface for the enduser to
set the priority of a specific interrupt(SPI/PPI)?
2. Is there any way to verify the higher priority interrupt will have
more dominant to be selected to the CPU (IOW, the priority is really
working) in case of multiple different interrupts asserted to the GIC
at the same time(some debug registers of GIC like GICD_REEMPT_CNT :-)
to record higher priority wins)?

Thanks