[PATCH] arm64: dts: ti: k3-j784s4: use ti,j7200-padconf compatible

[Francesco Dolcini]

Hello Thomas,
thanks for the update.

On Wed, Dec 04, 2024 at 10:08:43AM +0100, Thomas Richard wrote:
> On 11/19/24 20:01, Francesco Dolcini wrote:
> > Hello Thomas and TI folks,
> > 
> > On Wed, Nov 13, 2024 at 11:43:05AM +0100, Thomas Richard wrote:
> >> Like on j7200, pinctrl contexts shall be saved and restored during
> >> suspend-to-ram.
> >>
> >> So use ti,j7200-padconf compatible.
> >>
> >> Signed-off-by: Thomas Richard <thomas.richard at bootlin.com>
> >> ---
> >> Use ti,j7200-padconf compatible to save and restore pinctrl contexts during
> >> suspend-to-ram.
> >> ---
> >>  arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi       |  6 +++---
> >>  arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 12 ++++++------
> > 
> > Do j784s4 supports any kind of low power mode and/or suspend to ram? My
> > understanding was that this was not supported, but maybe there is some
> > details that was lost when I was told this information.
> 
> We are working on suspend-to-ram support for j7200 and j784s4.
> During suspend-to-ram the SoC is fully powered-off (thanks to the PMIC
> which powers off all the power rails except the DDR which is in
> self-refresh), like on j7200.
> Please let me know if you want more details.

ok, that's quite different from the common suspend-to-ram we use to have
implemented on other SoC. You would have some boot firmware (likely U-Boot)
code executing during resume, taking some different code path, in a similar way
to what it is being done for the partial-io support on am62p. It's going to be
more similar to hibernation from some point of view.

Do you expect to have this feature nicely integrated within the standard
suspend/resume "framework" in Linux?

It would be interesting to understand how to handle all the peripherals outside
the SoC, if you have reset/regulator controlled by GPIO from the SoC stuff will
happen as soon as the SoC is powered off since no one will drive this pins any
longer. From my understanding the only solution would be to not have such
regulator/reset connect to the SoC.

Francesco