[PATCH v4 2/2] arm64: dts: ti: k3-j722s-evm: Enable Inter-Processor Communication

[Kumar, Udit]

On 8/29/2024 11:39 AM, Beleswar Padhi wrote:
> From: Apurva Nandan <a-nandan at ti.com>
>
> The K3 J722S-EVM platform is based on the J722S SoC which has one
> single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN
> voltage domain, and two C71x DSP subsystems in MAIN voltage domain.
>
> The Inter-Processor communication between the A72 cores and these R5F

Should be A53 core not A72

> and DSP remote cores is achieved through shared memory and Mailboxes.
> Thus, add the memory carveouts and enable the mailbox clusters required
> for communication.
>
> Also, The remoteproc firmware like of R5F and DSPs in the MAIN voltage
> domain use timers. Therefore, change the status of the timer nodes to
> "reserved" to avoid any clash during booting of remotecores. Usage is
> described as below:
>
> 	+===================+=============+
> 	|  Remoteproc Node  | Timer Node  |
> 	+===================+=============+
> 	| main_r5fss0_core0 | main_timer0 |
> 	+-------------------+-------------+
> 	| c7x_0             | main_timer1 |
> 	+-------------------+-------------+
> 	| c7x_1             | main_timer2 |
> 	+-------------------+-------------+
>
> Signed-off-by: Apurva Nandan <a-nandan at ti.com>
> [ Enabled mailbox instances and Reserved timer nodes ]
> Signed-off-by: Beleswar Padhi <b-padhi at ti.com>
> [..]
>   
> +&mailbox0_cluster0 {
> +	status = "okay";
> +
> +	mbox_r5_0: mbox-r5-0 {

Could you choose name like mbox_wkup_r5_0 like other name of mbox


> +		ti,mbox-rx = <0 0 0>;
> +		ti,mbox-tx = <1 0 0>;
> +	};
> +};
> +
> +&mailbox0_cluster1 {
> +	status = "okay";
> +
> +	mbox_mcu_r5_0: mbox-mcu-r5-0 {
> +		ti,mbox-rx = <0 0 0>;
> +		ti,mbox-tx = <1 0 0>;
> [..]