[PATCH v3 4/4] arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC
Luo Jie
quic_luoj at quicinc.com
Tue Aug 27 05:46:02 PDT 2024
The CMN PLL clock controller allows selection of an input
clock rate from a defined set of input clock rates. It in-turn
supplies fixed rate output clocks to the hardware blocks that
provide ethernet functions, such as PPE (Packet Process Engine)
and connected switch or PHY.
Signed-off-by: Luo Jie <quic_luoj at quicinc.com>
---
arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 6 +++++-
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 ++++++++++++++++-
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
index 91e104b0f865..77e1e42083f3 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
@@ -3,7 +3,7 @@
* IPQ9574 RDP board common device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
@@ -164,6 +164,10 @@ &usb3 {
status = "okay";
};
+&cmn_pll_ref_clk {
+ clock-frequency = <48000000>;
+};
+
&xo_board_clk {
clock-frequency = <24000000>;
};
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 48dfafea46a7..1d7c863018c0 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -3,7 +3,7 @@
* IPQ9574 SoC device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,apss-ipq.h>
@@ -19,6 +19,11 @@ / {
#size-cells = <2>;
clocks {
+ cmn_pll_ref_clk: cmn-pll-ref-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -226,6 +231,16 @@ rpm_msg_ram: sram at 60000 {
reg = <0x00060000 0x6000>;
};
+ clock-controller at 9b000 {
+ compatible = "qcom,ipq9574-cmn-pll";
+ reg = <0x0009b000 0x800>;
+ clocks = <&cmn_pll_ref_clk>,
+ <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+ <&gcc GCC_CMN_12GPLL_SYS_CLK>;
+ clock-names = "ref", "ahb", "sys";
+ #clock-cells = <1>;
+ };
+
rng: rng at e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;
--
2.34.1
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