[PATCH v2 1/4] dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC

[Jie Luo]

On 8/22/2024 2:29 PM, Krzysztof Kozlowski wrote:
> On 21/08/2024 18:08, Jie Luo wrote:
>>
>>
>> On 8/21/2024 4:33 PM, Krzysztof Kozlowski wrote:
>>> On Tue, Aug 20, 2024 at 10:02:42PM +0800, Luo Jie wrote:
>>>> The CMN PLL controller provides clocks to networking hardware blocks
>>>> on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi,
>>>> and produces output clocks at fixed rates. These output rates are
>>>> predetermined, and are unrelated to the input clock rate. The output
>>>> clocks are supplied to the Ethernet hardware such as PPE (packet
>>>> process engine) and the externally connected switch or PHY device.
>>>>
>>>> Signed-off-by: Luo Jie <quic_luoj at quicinc.com>
>>>> ---
>>>>    .../bindings/clock/qcom,ipq9574-cmn-pll.yaml       | 70 ++++++++++++++++++++++
>>>>    include/dt-bindings/clock/qcom,ipq-cmn-pll.h       | 15 +++++
>>>>    2 files changed, 85 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
>>>> new file mode 100644
>>>> index 000000000000..7ad04b58a698
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
>>>> @@ -0,0 +1,70 @@
>>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Qualcomm CMN PLL Clock Controller on IPQ SoC
>>>> +
>>>> +maintainers:
>>>> +  - Bjorn Andersson <andersson at kernel.org>
>>>> +  - Luo Jie <quic_luoj at quicinc.com>
>>>> +
>>>> +description:
>>>> +  The CMN PLL clock controller expects a reference input clock.
>>>
>>> You did not explain what is CMN. Is this some sort of acronym?
>>
>> CMN is short form for 'common'. Since it is referred to as 'CMN'
>> PLL in the hardware programming guides, we wanted the driver name
>> to include it as well. The description can be updated as below to
>> clarify the name and purpose of this hardware block. Hope this is
>> fine.
>>
>> "The CMN PLL clock controller expects a reference input clock
>> from the on-board Wi-Fi, and supplies a number of fixed rate
>> output clocks to the Ethernet devices including PPE (packet
>> process engine) and the connected switch or PHY device. The
>> CMN (or 'common') PLL's only function is to enable clocks to
>> Ethernet hardware used with the IPQ SoC and does not include
>> any other function."
> 
> So the block is called "CMN" in hardware programming guide, without any
> explanation of the acronym?

Yes, I double checked again with our hardware team and the
documentation. CMN is just a short form of "common" with no additional
information in the guide.

Thanks for review.

> 
> Best regards,
> Krzysztof
>