[PATCH 3/3] dt-bindings: PCI: socionext,uniphier-pcie-ep: add top-level constraints

[Kunihiko Hayashi]

Hi Krzysztof,

On 2024/08/19 2:28, Krzysztof Kozlowski wrote:
> Properties with variable number of items per each device are expected to
> have widest constraints in top-level "properties:" block and further
> customized (narrowed) in "if:then:".  Add missing top-level constraints
> for clock-names and reset-names.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> ---
>   .../bindings/pci/socionext,uniphier-pcie-ep.yaml          | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git
> a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
> b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
> index f0d8e486a07d..93f3d0f4bb94 100644
> ---
> a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
> +++
> b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
> @@ -38,13 +38,17 @@ properties:
>       minItems: 1
>       maxItems: 2
>   
> -  clock-names: true
> +  clock-names:
> +    minItems: 1
> +    maxItems: 2
>   
>     resets:
>       minItems: 1
>       maxItems: 2
>   
> -  reset-names: true
> +  reset-names:
> +    minItems: 1
> +    maxItems: 2
>   
>     num-ib-windows:
>       const: 16

Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko at socionext.com>

I'd appreciate if it could be applied in devicetree or pci.

Thank you,

---
Best Regards
Kunihiko Hayashi