[PATCH v3] arm64: dts: imx93: update default value for snps,clk-csr

[Shawn Guo]

On Mon, Jul 15, 2024 at 08:17:22AM -0500, Shenwei Wang wrote:
> For the i.MX93 SoC, the default clock rate for the IP of STMMAC EQOS is
> 312.5 MHz. According to the following mapping table from the i.MX93
> reference manual, this clock rate corresponds to a CSR value of 6.
> 
>  0000: CSR clock = 60-100 MHz; MDC clock = CSR clock/42
>  0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62
>  0010: CSR clock = 20-35 MHz; MDC clock = CSR clock/16
>  0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26
>  0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102
>  0101: CSR clock = 250-300 MHz; MDC clock = CSR clock/124
>  0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204
>  0111: CSR clock = 500-800 MHz; MDC clock = CSR clock/324
> 
> Fixes: f2d03ba997cb ("arm64: dts: imx93: reorder device nodes")
> Signed-off-by: Shenwei Wang <shenwei.wang at nxp.com>

Applied, thanks!