[PATCH v2 06/14] arm64: dts: exynos: gs101: Add ufs, ufs-phy and ufs regulator dt nodes
André Draszik
andre.draszik at linaro.org
Thu Apr 25 05:02:55 PDT 2024
On Tue, 2024-04-23 at 21:49 +0100, Peter Griffin wrote:
> Enable the ufs controller, ufs phy and ufs regulator in device tree.
>
> Signed-off-by: Peter Griffin <peter.griffin at linaro.org>
> ---
> .../boot/dts/exynos/google/gs101-oriole.dts | 18 ++++++++++
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 36 +++++++++++++++++++
> 2 files changed, 54 insertions(+)
>
[...]
> +
> + ufs_0: ufs at 14700000 {
> + compatible = "google,gs101-ufs";
> + reg = <0x14700000 0x200>,
> + <0x14701100 0x200>,
> + <0x14780000 0xa000>,
> + <0x14600000 0x100>;
> + reg-names = "hci", "vs_hci", "unipro", "ufsp";
> + interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>,
> + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>,
> + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>,
> + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>,
> + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>,
> + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
> + clock-names = "core_clk", "sclk_unipro_main", "fmp",
> + "ufs_aclk", "ufs_pclk", "sysreg";
> + freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
The preferred order is pinctrl-0 before pinctrl-names (similar to clock-names and reg-names).
Other than that,
Acked-by: André Draszik <andre.draszik at linaro.org>
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