[bootwrapper PATCH 2/2] aarch64: Disable trapping into EL3 while accessing FEAT_FGT2 registers

[Anshuman Khandual]

This disables trapping into EL3 while accessing Fine Grained Traps Enable 2
(i.e FEAT_FGT2) registers such as HDFGRTR2_EL2, HDFGWTR2_EL2, HFGITR2_EL2,
HFGRTR2_EL2 and HFGWTR2_EL2 via setting SCR_EL3.FGTEN2. But first ensure
that FEAT_FGT2 feature is implemented looking into ID_AA64MMFR0_EL1.

Signed-off-by: Anshuman Khandual <anshuman.khandual at arm.com>
---
 arch/aarch64/include/asm/cpu.h | 1 +
 arch/aarch64/init.c            | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 124ef91..56f319a 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -57,6 +57,7 @@
 #define SCR_EL3_EnTP2			BIT(41)
 #define SCR_EL3_TCR2EN			BIT(43)
 #define SCR_EL3_PIEN			BIT(45)
+#define SCR_EL3_FGTEN2			BIT(59)
 
 #define HCR_EL2_RES1			BIT(1)
 
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index 37cb45f..557266b 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -68,6 +68,9 @@ void cpu_init_el3(void)
 	if (mrs_field(ID_AA64MMFR0_EL1, FGT))
 		scr |= SCR_EL3_FGTEN;
 
+	if (mrs_field(ID_AA64MMFR0_EL1, FGT) >= 2)
+		scr |= SCR_EL3_FGTEN2;
+
 	if (mrs_field(ID_AA64MMFR0_EL1, ECV) >= 2)
 		scr |= SCR_EL3_ECVEN;
 
-- 
2.25.1