[PATCH 3/3] arm64: dts: marvell: espressobin-ultra: fix Ethernet Switch unit address

[Krzysztof Kozlowski]

The Espressobin Ultra DTS includes Espressobin DTSI which defines
ethernet-switch at 1 node.  The Ultra DTS overrides "reg" to 3, but that
leaves still old unit address which conflicts with the new phy at 1 node
(W=1 dtc warning):

  armada-3720-espressobin.dtsi:148.29-203.4: Warning (unique_unit_address_if_enabled): /soc/internal-regs at d0000000/mdio at 32004/ethernet-switch at 1: duplicate unit-address (also used in node /soc/internal-regs at d0000000/mdio at 32004/ethernet-phy at 1)

Fix this by deleting ethernet-switch at 1 node and merging original node
with code from Ultra DTS into new ethernet-switch at 3.

Signed-off-by: Krzysztof Kozlowski <krzk at kernel.org>

---

Not tested on hardware.
---
 .../marvell/armada-3720-espressobin-ultra.dts | 104 +++++++++++-------
 1 file changed, 67 insertions(+), 37 deletions(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
index 870bb380a40a..b3cc2b7b5d19 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
@@ -114,54 +114,84 @@ &usb3 {
 };
 
 &mdio {
+	/* Switch is @3, not @1 */
+	/delete-node/ ethernet-switch at 1;
 	extphy: ethernet-phy at 1 {
 		reg = <1>;
 
 		reset-gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
 	};
-};
 
-&switch0 {
-	reg = <3>;
+	switch0: ethernet-switch at 3 {
+		compatible = "marvell,mv88e6085";
+		reg = <3>;
 
-	reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>;
+		dsa,member = <0 0>;
 
-	ethernet-ports {
-		switch0port1: ethernet-port at 1 {
-			reg = <1>;
-			label = "lan0";
-			phy-handle = <&switch0phy0>;
+		ethernet-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			switch0port0: ethernet-port at 0 {
+				reg = <0>;
+				label = "cpu";
+				ethernet = <&eth0>;
+				phy-mode = "rgmii-id";
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			switch0port1: ethernet-port at 1 {
+				reg = <1>;
+				label = "lan0";
+				phy-handle = <&switch0phy0>;
+			};
+
+			switch0port2: ethernet-port at 2 {
+				reg = <2>;
+				label = "lan1";
+				phy-handle = <&switch0phy1>;
+			};
+
+			switch0port3: ethernet-port at 3 {
+				reg = <3>;
+				label = "lan2";
+				phy-handle = <&switch0phy2>;
+			};
+
+			switch0port4: ethernet-port at 4 {
+				reg = <4>;
+				label = "lan3";
+				phy-handle = <&switch0phy3>;
+			};
+
+			switch0port5: ethernet-port at 5 {
+				reg = <5>;
+				label = "wan";
+				phy-handle = <&extphy>;
+				phy-mode = "sgmii";
+			};
 		};
 
-		switch0port2: ethernet-port at 2 {
-			reg = <2>;
-			label = "lan1";
-			phy-handle = <&switch0phy1>;
-		};
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
 
-		switch0port3: ethernet-port at 3 {
-			reg = <3>;
-			label = "lan2";
-			phy-handle = <&switch0phy2>;
-		};
-
-		switch0port4: ethernet-port at 4 {
-			reg = <4>;
-			label = "lan3";
-			phy-handle = <&switch0phy3>;
-		};
-
-		switch0port5: ethernet-port at 5 {
-			reg = <5>;
-			label = "wan";
-			phy-handle = <&extphy>;
-			phy-mode = "sgmii";
-		};
-	};
-
-	mdio {
-		switch0phy3: ethernet-phy at 14 {
-			reg = <0x14>;
+			switch0phy0: ethernet-phy at 11 {
+				reg = <0x11>;
+			};
+			switch0phy1: ethernet-phy at 12 {
+				reg = <0x12>;
+			};
+			switch0phy2: ethernet-phy at 13 {
+				reg = <0x13>;
+			};
+			switch0phy3: ethernet-phy at 14 {
+				reg = <0x14>;
+			};
 		};
 	};
 };
-- 
2.34.1