[PATCH] arm64: mm: Optimize querying asid from reserved_asids

Will Deacon will at kernel.org
Fri Sep 29 09:51:21 PDT 2023


On Wed, Sep 27, 2023 at 01:51:06PM +0800, Guo Hui wrote:
> Move reserved_asids updates into function flush_context. When
> asid_generation increases, reserved_asids are updated synchronously.
> The execution frequency of function flush_context is far less than
> that of function check_update_reserved_asid. In function
> check_update_reserved_asid, you only need to query whether it is
> in reserved_asids based on the new newasid, and there is no need
> to update it.
> 
> In the function check_update_reserved_asid, among all the times
> reserved_asids are hit, the probability that newasid is equal to
> the reserved_asids of the current CPU is about greater than 70%.

Do you have any performance numbers to justify this change?

> diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
> index 188197590fc9..76e0beb14466 100644
> --- a/arch/arm64/mm/context.c
> +++ b/arch/arm64/mm/context.c
> @@ -101,7 +101,7 @@ static void set_reserved_asid_bits(void)
>  #define asid_gen_match(asid) \
>  	(!(((asid) ^ atomic64_read(&asid_generation)) >> asid_bits))
>  
> -static void flush_context(void)
> +static void flush_context(u64 generation)
>  {
>  	int i;
>  	u64 asid;
> @@ -120,6 +120,8 @@ static void flush_context(void)
>  		 */
>  		if (asid == 0)
>  			asid = per_cpu(reserved_asids, i);
> +
> +		asid = generation | (asid & ~ASID_MASK);

I'm struggling to see how this is safe with multiple rollovers. For
example, if we have the following sequence of events on one CPU:

1. Task A runs with ASID 42
2. Context switch to Task C with ASID 66
3. A rollover occurs
4. Task B runs for the first time; gets allocated ASID 42
5. Another rollover occurs
6. Task A runs

Won't task A get ASID 42, even though that's reserved for task B?

But this code is subtle, so maybe I missed something.

Also, if we change this, then you should update the TLA+ model over at

https://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/kernel-tla.git/tree/asidalloc.tla

Cheers,

Will



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