[PATCH 2/2] dt-bindings: arm,coresight-cti: Add missing additionalProperties on child nodes

[Mike Leach]

On Mon, 25 Sept 2023 at 23:05, Rob Herring <robh at kernel.org> wrote:
>
> Just as unevaluatedProperties or additionalProperties are required at
> the top level of schemas, they should (and will) also be required for
> child node schemas. That ensures only documented properties are
> present for any node.
>
> Adding additionalProperties constraint on 'trig-conns' nodes results in
> warnings that 'cpu' and 'arm,cs-dev-assoc' are not allowed. These are
> already defined for the parent node, but need to be duplicated for the
> child node. Drop the free form description that the properties also apply
> to the child nodes.
>
> Signed-off-by: Rob Herring <robh at kernel.org>
> ---
>  .../bindings/arm/arm,coresight-cti.yaml       | 33 ++++++++++++++-----
>  1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
> index b9bdfc8969cd..2d5545a2b49c 100644
> --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
> @@ -93,9 +93,7 @@ properties:
>
>    cpu:
>      description:
> -      Handle to cpu this device is associated with. This must appear in the
> -      base cti node if compatible string arm,coresight-cti-v8-arch is used,
> -      or may appear in a trig-conns child node when appropriate.
> +      Handle to cpu this CTI is associated with.
>
>    power-domains:
>      maxItems: 1
> @@ -112,12 +110,12 @@ properties:
>      description:
>        defines a phandle reference to an associated CoreSight trace device.
>        When the associated trace device is enabled, then the respective CTI
> -      will be enabled. Use in a trig-conns node, or in CTI base node when
> -      compatible string arm,coresight-cti-v8-arch used. If the associated
> -      device has not been registered then the node name will be stored as
> -      the connection name for later resolution. If the associated device is
> -      not a CoreSight device or not registered then the node name will remain
> -      the connection name and automatic enabling will not occur.
> +      will be enabled. Use in CTI base node when compatible string
> +      arm,coresight-cti-v8-arch used. If the associated device has not been
> +      registered then the node name will be stored as the connection name for
> +      later resolution. If the associated device is not a CoreSight device or
> +      not registered then the node name will remain the connection name and
> +      automatic enabling will not occur.
>
>    # size cells and address cells required if trig-conns node present.
>    "#size-cells":
> @@ -129,6 +127,8 @@ properties:
>  patternProperties:
>    '^trig-conns@([0-9]+)$':
>      type: object
> +    additionalProperties: false
> +
>      description:
>        A trigger connections child node which describes the trigger signals
>        between this CTI and another hardware device. This device may be a CPU,
> @@ -140,6 +140,21 @@ patternProperties:
>        reg:
>          maxItems: 1
>
> +      cpu:
> +        description:
> +          Handle to cpu this trigger connection is associated with.
> +
> +      arm,cs-dev-assoc:
> +        $ref: /schemas/types.yaml#/definitions/phandle
> +        description:
> +          defines a phandle reference to an associated CoreSight trace device.
> +          When the associated trace device is enabled, then the respective CTI
> +          will be enabled. If the associated device has not been registered
> +          then the node name will be stored as the connection name for later
> +          resolution. If the associated device is not a CoreSight device or
> +          not registered then the node name will remain the connection name
> +          and automatic enabling will not occur.
> +
>        arm,trig-in-sigs:
>          $ref: /schemas/types.yaml#/definitions/uint32-array
>          minItems: 1
> --
> 2.40.1
>

Reviewed-by: Mike Leach <mike.leach at linaro.org>

-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK