[PATCH v7 3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver

[Havalige, Thippeswamy]

Hi Bjorn/ Lorenzo/Krzysztof,

Can you please provide any update on this patch series.

Regards,
Thippeswamy H

> -----Original Message-----
> From: Bjorn Helgaas <helgaas at kernel.org>
> Sent: Wednesday, September 6, 2023 10:55 PM
> To: Havalige, Thippeswamy <thippeswamy.havalige at amd.com>
> Cc: linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> bhelgaas at google.com; krzysztof.kozlowski+dt at linaro.org;
> devicetree at vger.kernel.org; linux-pci at vger.kernel.org; lpieralisi at kernel.org;
> robh at kernel.org; conor+dt at kernel.org; Simek, Michal
> <michal.simek at amd.com>; Gogada, Bharat Kumar
> <bharat.kumar.gogada at amd.com>
> Subject: Re: [PATCH v7 3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver
> 
> On Wed, Aug 30, 2023 at 02:37:07PM +0530, Thippeswamy Havalige wrote:
> > Add support for Xilinx XDMA Soft IP core as Root Port.
> >
> > The Zynq UltraScale+ MPSoCs devices support XDMA soft IP module in
> > programmable logic.
> >
> > The integrated XDMA soft IP block has integrated bridge function that
> > can act as PCIe Root Port.
> 
> > +	if (!pci_is_root_bus(bus)) {
> > +		/* Checking whether the link is up is the last line of
> > +		 * defense, and this check is inherently racy by definition.
> > +		 * Sending a PIO request to a downstream device when the
> link is
> > +		 * down causes an unrecoverable error, and a reset of the
> entire
> > +		 * PCIe controller will be needed. We can reduce the
> likelihood
> > +		 * of that unrecoverable error by checking whether the link is
> > +		 * up, but we can't completely prevent it because the link may
> > +		 * go down between the link-up check and the PIO request.
> > +		 */
> 
> Looks fine to me.  If Lorenzo or Krzysztof thinks this is ready to go, maybe they
> will tidy the comment above, i.e.,
> 
>   /*
>    * Checking whether ...