[PATCH 00/13] imx8mp: first clock propagation attempt (for LVDS)

[Benjamin Bara]

Hi Adam!

On Mon, 18 Sept 2023 at 07:00, Adam Ford <aford173 at gmail.com> wrote:
> On Sun, Sep 17, 2023 at 3:40 PM Benjamin Bara <bbara93 at gmail.com> wrote:
> > The idea:
> > Enable CLK_SET_RATE_PARENT, at least for media_disp2_pix and media_ldb.
> > When this is done, ensure that the pll1443x can be re-configured,
> > meaning it ensures that an already configured rate (crtc rate) is still
> > supported when a second child requires a different rate (lvds rate). As
>
> Have you tested with the DSI as well?  If memory servers, the DSI
> clock and the LVDS clock are both clocked from the same video_pll.  At
> one time, I had done some experimentation with trying the DSI
> connected to an HDMI bridge chip connected to a monitor and the LVDS
> was connected to a display panel with a static resolution and refresh
> rate.  For my LVDS display, it needs 30MHz to display properly, but
> various HDMI resolutions needed values that were not evenly divisible
> by 30MHz which appeared to cause display sync issues when trying to
> share a clock that was trying to dynamically adjust for two different
> displays especially when trying to change the resoltuion of the HDMI
> display to various values for different resolutions.

Unfortunately I haven't. I think if you have the use case to support
different "run-time-dynamic" (HDMI) rates in parallel with a static
(LVDS) rate, it probably makes sense (for now) to just use a LVDS panel
which can be feeded from one of the static PLLs directly and do a manual
re-parenting in the dt. The manual re-parenting could be replaced by an
automated re-parenting in the composite driver. When I think about it,
it might make sense to extend clk-divider's clk_divider_bestdiv()[1]
(which is currently used by the composite-8m) with a "find the best
parent" implementation, something like:
1. are we in range if we divide the active parent with all possible
   dividers? (already existing)
2. are we in range if we switch to a different parent and divide it with
   all possible dividers?
3. are we in range if we re-configure a possible parent (and switch to
   it)?

Steps 2 & 3 are e.g. implemented by at91's clk-master[2]. There are
maybe also "smarter" solutions to the problem beside trying every
possibility. Anyways, we already have a CLK_SET_RATE_NO_REPARENT which
would indicate if we are allowed to do so.

For static use cases involving both, I would probably (for now) go with
a hard-assigned, tested clock rate in the dt. IMHO, this should always
work as fall-back.

Regards,
Benjamin

[1] https://elixir.bootlin.com/linux/v6.5.3/source/drivers/clk/clk-divider.c#L304
[2] https://elixir.bootlin.com/linux/v6.5.3/source/drivers/clk/at91/clk-master.c#L586