[PATCH v2 4/7] arm64: dts: ti: k3-j784s4-main: Add the main domain watchdog instances

[J, KEERTHY]

On 9/7/2023 7:44 PM, Kumar, Udit wrote:
> Thanks Keerthy,
> 
> On 9/7/2023 5:22 PM, Keerthy wrote:
>> There are totally 19 instances of watchdog module. One each for the
>> 8 A72 cores, one each for the 4 C7x cores, 1 for the GPU, 1 each
>> for the 6 R5F cores in the main domain. Keeping only the A72 instances
>> enabled and disabling the rest by default.
>>
>> Signed-off-by: Keerthy <j-keerthy at ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 182 +++++++++++++++++++++
>>   1 file changed, 182 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi 
>> b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> index 7f7eab348520..66ab947a1081 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> @@ -1574,4 +1574,186 @@
>>           reg = <0x00 0x700000 0x00 0x1000>;
>>           ti,esm-pins = <688>, <689>;
>>       };
>> +
>> +    watchdog0: watchdog at 2200000 {
>> +        compatible = "ti,j7-rti-wdt";
>> +        reg = <0x00 0x2200000 0x00 0x100>;
>> +        clocks = <&k3_clks 348 1>;
>> +        power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
>> +        assigned-clocks = <&k3_clks 348 0>;
>> +        assigned-clock-parents = <&k3_clks 348 4>;
>> +    };
> 
> In ESM, patch I see only output of 2 watchdog in cascaded for reset.
> 
> if you want to keep enable other wdt, then IMO they should be able to 
> reset the core/SOC
> 
> on timeout

I can add the other ESM events to the ESM node to enable that. I will 
wait if there are more comments. If this is the only one comment i will 
post a v3 of the esm patch.

- Keerthy
> 
> 
>> +
>> +    [..]};