[RFC PATCH 1/2] dt-bindings: PCI: ti,j721e-pci-*: Add "ti,syscon-pcie-refclk-out" property

[Krzysztof Kozlowski]

On 05/09/2023 13:48, Achal Verma wrote:
> Added "ti,syscon-pcie-refclk-out" property to specify the ACSPCIE clock
> buffer register offset in SYSCON, which would be used to enable serdes
> reference clock output.
> 
> Signed-off-by: Achal Verma <a-verma1 at ti.com>
> ---
>  .../bindings/pci/ti,j721e-pci-host.yaml       | 53 +++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> index a2c5eaea57f5..27bdc52282c4 100644
> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> @@ -44,6 +44,18 @@ properties:
>            - description: pcie_ctrl register offset within SYSCON
>      description: Specifier for configuring PCIe mode and link speed.
>  
> +  ti,syscon-pcie-refclk-out:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: Phandle to the SYSCON entry
> +          - description: lock2_kick0 register offset within SYSCON
> +          - description: lock2_kick1 register offset within SYSCON
> +          - description: acspcie_ctrl register offset within SYSCON
> +          - description: pcie_refclk_clksel register offset within SYSCON
> +          - description: clock source index to source ref clock
> +    description: Specifier for enabling ACSPCIe clock buffer for reference clock output.

No, syscon is not a way to avoid creating clock/reset/power controllers.
NAK.


>    power-domains:
>      maxItems: 1
>  
> @@ -99,6 +111,7 @@ required:
>    - reg
>    - reg-names
>    - ti,syscon-pcie-ctrl
> +  - ti,syscon-pcie-refclk-out

So an ABI break?

>    - max-link-speed
>    - num-lanes
>    - power-domains
> @@ -153,3 +166,43 @@ examples:
>              dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>          };
>      };
> +
> +  -
> +    #include <dt-bindings/mux/mux.h>
> +    #include <dt-bindings/mux/ti-serdes.h>
> +    #include <dt-bindings/phy/phy.h>
> +    #include <dt-bindings/phy/phy-ti.h>
> +
> +    bus {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        pcie1_rc: pcie at 2910000 {
> +                compatible = "ti,j784s4-pcie-host";
> +                reg = <0x00 0x02910000 0x00 0x1000>,

No need for new example. It's anyway wrongly formatted...


Best regards,
Krzysztof