[RFC 02/12] arm_mpam: resctrl: Detect priority partitioning capability

Jonathan Cameron Jonathan.Cameron at Huawei.com
Fri Sep 1 05:30:19 PDT 2023


On Tue, 15 Aug 2023 20:57:02 +0530
Amit Singh Tomar <amitsinght at marvell.com> wrote:

> ARM MPAM supports different control that can be applied to different
> resources in the system, for instance priority partitioning control
> where priority value is generated from one MSC, propagates over
> interconnect to other MSC (known as downstream priority), or can be
> applied within an MSC for internal operations.

Hi Amit,

This talks about INTPRI as well as DSPRI, but only checks for DSPRI.
I couldn't work out why my INTPRI test wasn't resulting in anything
new turning up in schemata.

Should make that clear  However even better would be to enable both
and we definitely want an interface that allows for either or both.

Jonathan

> 
> This change lets the resctrl know the about MSC's priority partitioning
> capability.
> 
> Signed-off-by: Amit Singh Tomar <amitsinght at marvell.com>
> ---
>  drivers/platform/mpam/mpam_resctrl.c | 14 ++++++++++++++
>  include/linux/resctrl.h              |  4 ++++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/drivers/platform/mpam/mpam_resctrl.c b/drivers/platform/mpam/mpam_resctrl.c
> index 1dbfb6f6dd34..09618d9ceb1d 100644
> --- a/drivers/platform/mpam/mpam_resctrl.c
> +++ b/drivers/platform/mpam/mpam_resctrl.c
> @@ -435,6 +435,16 @@ static bool cache_has_usable_cpor(struct mpam_class *class)
>  	return (class->props.cpbm_wd <= RESCTRL_MAX_CBM);
>  }
>  
> +static bool cache_has_usable_priority_part(struct mpam_class *class)
> +{
> +	struct mpam_props *cprops = &class->props;
> +
> +	if (!mpam_has_feature(mpam_feat_dspri_part, cprops))
> +		return false;
> +
> +	return (class->props.dspri_wd <= RESCTRL_MAX_DSPRI);
> +}
> +
>  static bool cache_has_usable_csu(struct mpam_class *class)
>  {
>  	struct mpam_props *cprops;
> @@ -691,6 +701,7 @@ static int mpam_resctrl_resource_init(struct mpam_resctrl_res *res)
>  	    res->resctrl_res.rid == RDT_RESOURCE_L3) {
>  		bool has_csu = cache_has_usable_csu(class);
>  		bool has_mbwu = class_has_usable_mbwu(class);
> +		bool has_ppart = cache_has_usable_priority_part(class);
>  
>  		/* TODO: Scaling is not yet supported */
>  		r->cache.cbm_len = class->props.cpbm_wd;
> @@ -718,6 +729,9 @@ static int mpam_resctrl_resource_init(struct mpam_resctrl_res *res)
>  			exposed_alloc_capable = true;
>  		}
>  
> +		if (has_ppart)
> +			r->priority_cap = true;
> +
>  		/*
>  		 * MBWU counters may be 'local' or 'total' depending on where
>  		 * they are in the topology. If The counter is on the L3, its
> diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h
> index 3ad308e9e226..a98ba5828211 100644
> --- a/include/linux/resctrl.h
> +++ b/include/linux/resctrl.h
> @@ -38,6 +38,8 @@ int proc_resctrl_show(struct seq_file *m,
>   */
>  #define RESCTRL_MAX_CBM			32
>  
> +#define RESCTRL_MAX_DSPRI               63
> +
>  /* The format for packing fields into the u64 'id' exposed to user-space */
>  #define RESCTRL_ID_CLOSID	GENMASK_ULL(31, 0)
>  #define RESCTRL_ID_RMID		GENMASK_ULL(63, 32)
> @@ -195,6 +197,7 @@ struct resctrl_membw {
>   * @rid:		The index of the resource
>   * @alloc_capable:	Is allocation available on this machine
>   * @mon_capable:	Is monitor feature available on this machine
> + * @priority_capable:   Is priority partitioning feature available on this machine
>   * @num_rmid:		Number of RMIDs available
>   * @cache_level:	Which cache level defines scope of this resource
>   * @cache:		Cache allocation related data
> @@ -212,6 +215,7 @@ struct rdt_resource {
>  	int			rid;
>  	bool			alloc_capable;
>  	bool			mon_capable;
> +	bool                    priority_cap;
>  	int			num_rmid;
>  	int			cache_level;
>  	struct resctrl_cache	cache;




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