[PATCH v3] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs.

[Marc Zyngier]

On Mon, 30 Oct 2023 07:00:20 +0000,
Fang Xiang <fangxiang3 at xiaomi.com> wrote:
> 
> In non-coherent GIC design, ITS tables should be clean and flushed
> to the PoV of the ITS before writing GITS_BASER<n> registers, otherwise
> the ITS would read dirty tables and lead to UNPREDICTABLE behaviors.
> 
> The ITS always got clean tables in initialization with this fix, by
> observing the signals from GIC.
> 
> Furthermore, hoist the quirked non-shareable attributes earlier to
> save effort in tables setup.
> 
> Signed-off-by: Marc Zyngier <maz at kernel.org>

Please read the documentation[1]. You cannot use my own SoB yourself.
*I* put it on patches *I* author, but you don't get to do that unless
you put me as the author (which isn't the case here). The original
suggestion from Thomas was 'Originally-by:', and 'Suggested-by:' would
work as well.

> Signed-off-by: Fang Xiang <fangxiang3 at xiaomi.com>
> Tested-by: Fang Xiang <fangxiang3 at xiaomi.com>
> 
> Link to v2:
> https://lore.kernel.org/all/20231027031007.2088-1-fangxiang3@xiaomi.com/
> 
> Link to v1:
> https://lore.kernel.org/all/20231026020116.4238-1-fangxiang3@xiaomi.com/
> 
> v2 -> v3:
>     - Add 'Signed-off-by' trailer for original author Marc
>     - Expand commit message with testing result
> 
> v1 -> v2:
>     - Flush ITS tables before writing GITS_BASER<n> registers
>     - Hoist the quirked non-shareable attributes earlier

All this needs to go as a note *under* the '---' line.

Thanks,

	M.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst#n396

-- 
Without deviation from the norm, progress is not possible.