[PATCH] ARM: dts: usr8200: Fix phy registers

[Linus Walleij]

The MV88E6060 switch has internal PHY registers at MDIO
addresses 0x00..0x04. Tie each port to the corresponding
PHY.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
SoC folks: please apply this directly to DTS files or
fixes whatever comes first.
---
 .../intel/ixp/intel-ixp42x-usrobotics-usr8200.dts  | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
index 90fd51b36e7d..2c89db34c8d8 100644
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
@@ -165,6 +165,24 @@ mdio {
 				#address-cells = <1>;
 				#size-cells = <0>;
 
+				/*
+				 * PHY 0..4 are internal to the MV88E6060 switch but appear
+				 * as independent devices.
+				 */
+				phy0: ethernet-phy at 0 {
+					reg = <0>;
+				};
+				phy1: ethernet-phy at 1 {
+					reg = <1>;
+				};
+				phy2: ethernet-phy at 2 {
+					reg = <2>;
+				};
+				phy3: ethernet-phy at 3 {
+					reg = <3>;
+				};
+
+				/* Altima AMI101L used by the WAN port */
 				phy9: ethernet-phy at 9 {
 					reg = <9>;
 				};
@@ -181,21 +199,25 @@ ports {
 						port at 0 {
 							reg = <0>;
 							label = "lan1";
+							phy-handle = <&phy0>;
 						};
 
 						port at 1 {
 							reg = <1>;
 							label = "lan2";
+							phy-handle = <&phy1>;
 						};
 
 						port at 2 {
 							reg = <2>;
 							label = "lan3";
+							phy-handle = <&phy2>;
 						};
 
 						port at 3 {
 							reg = <3>;
 							label = "lan4";
+							phy-handle = <&phy3>;
 						};
 
 						port at 5 {

---
base-commit: 9f3539d6b794040c3054acf1f547c41fb381a0fc
change-id: 20231020-ixp4xx-usr8200-dtsfix-ed058cfd5d07

Best regards,
-- 
Linus Walleij <linus.walleij at linaro.org>