[PATCH v5 RESEND 0/4] increase ecam size value to discover 256 buses during

[Havalige, Thippeswamy]

Hi Bjorn,

Can you please provide an update on this patch series.

Regards,
Thippeswamy H

> -----Original Message-----
> From: Thippeswamy Havalige <thippeswamy.havalige at amd.com>
> Sent: Monday, October 16, 2023 10:41 AM
> To: linux-pci at vger.kernel.org; devicetree at vger.kernel.org; linux-
> kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Cc: bhelgaas at google.com; lpieralisi at kernel.org; kw at linux.com;
> robh at kernel.org; krzysztof.kozlowski+dt at linaro.org; colnor+dt at kernel.org;
> Havalige, Thippeswamy <thippeswamy.havalige at amd.com>; Simek, Michal
> <michal.simek at amd.com>; Gogada, Bharat Kumar
> <bharat.kumar.gogada at amd.com>
> Subject: [PATCH v5 RESEND 0/4] increase ecam size value to discover 256
> buses during
> 
> Current driver is supports up to 16 buses. The following code fixes to support
> up to 256 buses.
> 
> update "NWL_ECAM_VALUE_DEFAULT " to 16  can access up to 256MB ECAM
> region to detect 256 buses.
> 
> Update ecam size to 256MB in device tree binding example.
> 
> Remove unwanted code.
> 
> Thippeswamy Havalige (4):
>   PCI: xilinx-nwl: Remove unnecessary code which updates primary,
>     secondary and sub-ordinate bus numbers
>   dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example
>   PCI: xilinx-nwl: Rename ECAM size default macro
>   PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses
> 
>  .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml |  2 +-
>  drivers/pci/controller/pcie-xilinx-nwl.c       | 18 +++---------------
>  2 files changed, 4 insertions(+), 16 deletions(-)
> 
> --
> 2.25.1