[EXT] Re: [PATCH 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property

[Linu Cherian]

Hi Mike,

> -----Original Message-----
> From: Mike Leach <mike.leach at linaro.org>
> Sent: Friday, October 6, 2023 4:33 PM
> To: Linu Cherian <lcherian at marvell.com>
> Cc: suzuki.poulose at arm.com; james.clark at arm.com; leo.yan at linaro.org;
> linux-arm-kernel at lists.infradead.org; coresight at lists.linaro.org; linux-
> kernel at vger.kernel.org; robh+dt at kernel.org;
> krzysztof.kozlowski+dt at linaro.org; conor+dt at kernel.org;
> devicetree at vger.kernel.org; Sunil Kovvuri Goutham
> <sgoutham at marvell.com>; George Cherian <gcherian at marvell.com>
> Subject: [EXT] Re: [PATCH 1/7] dt-bindings: arm: coresight-tmc: Add
> "memory-region" property
> 
> External Email
> 
> ----------------------------------------------------------------------
> Hi Linu
> 
> On Fri, 29 Sept 2023 at 14:38, Linu Cherian <lcherian at marvell.com> wrote:
> >
> > memory-region 0: Reserved trace buffer memory
> >
> >   TMC ETR: When available, use this reserved memory region for
> >   trace data capture. Same region is used for trace data
> >   retention after a panic or watchdog reset.
> >
> >   TMC ETF: When available, use this reserved memory region for
> >   trace data retention synced from internal SRAM after a panic or
> >   watchdog reset.
> >
> > memory-region 1: Reserved meta data memory
> >
> >   TMC ETR, ETF: When available, use this memory for register
> >   snapshot retention synced from hardware registers after a panic
> >   or watchdog reset.
> >
> > Signed-off-by: Linu Cherian <lcherian at marvell.com>
> > ---
> >  .../bindings/arm/arm,coresight-tmc.yaml       | 19 +++++++++++++++++++
> >  1 file changed, 19 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> > b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> > index cb8dceaca70e..45ca4d02d73e 100644
> > --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> > @@ -101,6 +101,22 @@ properties:
> >            and ETF configurations.
> >          $ref: /schemas/graph.yaml#/properties/port
> >
> > +  memory-region:
> > +    items:
> > +      - description: Reserved trace buffer memory for ETR and ETF sinks.
> > +          For ETR, this reserved memory region is used for trace data capture.
> > +          Same region is used for trace data retention as well after a panic
> > +          or watchdog reset.
> > +          For ETF, this reserved memory region is used for retention of trace
> > +          data synced from internal SRAM after a panic or watchdog reset.
> > +
> 
> Is there a valid use case for ETR where we use these areas when there is not
> a panic/reset situation?
> 

Currently its meant to be used only for the panic/reset situations and gets enabled only with a special buffer mode.

> Either way - the description should perhaps mention that these areas are
> only used if specifically selected by the driver - the default memory usage
> models for ETR / perf are otherwise unaltered.
	
Ack. 

> 
> > +      - description: Reserved meta data memory. Used for ETR and ETF sinks.
> > +
> > +  memory-region-names:
> > +    items:
> > +      - const: trace-mem
> > +      - const: metadata-mem
> > +
> 
> Is there a constraint required here? If we are using the memory area for
> trace in a panic situation, then we must have the meta data memory area
> defined?
> Perhaps a set of names such as "etr-trace-mem", "panic-trace-mem" ,
> "panic-metadata-mem", were the first is for general ETR trace in non-panic
> situation and then constrain the "panic-" areas to appear together.
> The "etr-trace-mem", "panic-trace-mem" could easily point to the same
> area.
> 
As noted above, we do not have other generic use case for these reserved regions now.
Hence two regions/names, panic-trace-mem and panic-metadata-mem with constraints kept as
 minItems: 2 and maxItems: 2 would suffice ?


> >  required:
> >    - compatible
> >    - reg
> > @@ -115,6 +131,9 @@ examples:
> >      etr at 20070000 {
> >          compatible = "arm,coresight-tmc", "arm,primecell";
> >          reg = <0x20070000 0x1000>;
> > +        memory-region = <&etr_trace_mem_reserved>,
> > +                       <&etr_mdata_mem_reserved>;
> > +        memory-region-names = "trace-mem", "metadata-mem";
> >
> >          clocks = <&oscclk6a>;
> >          clock-names = "apb_pclk";
> > --
> > 2.34.1
> >
> 
> 
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK