[PATCH v2 11/28] clk: renesas: rzg2l: add a divider clock for RZ/G3S

[Geert Uytterhoeven]

Hi Claudiu,

On Wed, Oct 4, 2023 at 2:30 PM Geert Uytterhoeven <geert at linux-m68k.org> wrote:
> On Fri, Sep 29, 2023 at 7:39 AM Claudiu <claudiu.beznea at tuxon.dev> wrote:
> > From: Claudiu Beznea <claudiu.beznea.uj at bp.renesas.com>
> >
> > Add a divider clock driver for RZ/G3S. This will be used in RZ/G3S
> > by SDHI, SPI, OCTA, I, I2, I3, P0, P1, P2, P3 core clocks.
> > The divider has some limitation for SDHI and OCTA clocks:
> > - SD div cannot be 1 if parent rate is 800MHz
> > - OCTA div cannot be 1 if parent rate is 400MHz
> > For these clocks a notifier could be registered from platform specific
> > clock driver and proper actions are taken before clock rate is changed,
> > if needed.
> >
> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj at bp.renesas.com>
> > ---
> >
> > Changes in v2:
> > - removed DIV_NOTIF macro

> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c

> > +static struct clk * __init
> > +rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks,
> > +                          void __iomem *base, struct rzg2l_cpg_priv *priv)
> > +{
> > +       struct div_hw_data *div_hw_data;
> > +       struct clk_init_data init = {};
> > +       const struct clk_div_table *clkt;
> > +       struct clk_hw *clk_hw;
> > +       const struct clk *parent;
> > +       const char *parent_name;
> > +       u32 max;
> > +       int ret;
> > +
> > +       parent = clks[core->parent & 0xffff];
> > +       if (IS_ERR(parent))
> > +               return ERR_CAST(parent);
> > +
> > +       parent_name = __clk_get_name(parent);
> > +
> > +       div_hw_data = devm_kzalloc(priv->dev, sizeof(*div_hw_data), GFP_KERNEL);
> > +       if (!div_hw_data)
> > +               return ERR_PTR(-ENOMEM);
> > +
> > +       init.name = core->name;
> > +       init.flags = core->flag;
> > +       init.ops = &rzg3s_div_clk_ops;
> > +       init.parent_names = &parent_name;
> > +       init.num_parents = 1;
> > +
> > +       /* Get the maximum divider to retrieve div width. */
> > +       for (clkt = core->dtable; clkt->div; clkt++) {
> > +               if (max < clkt->div)
>
> "max" is used uninitialized
>
> > +                       max = clkt->div;
> > +       }
> > +
> > +       div_hw_data->hw_data.priv = priv;
> > +       div_hw_data->hw_data.conf = core->conf;
> > +       div_hw_data->hw_data.sconf = core->sconf;
> > +       div_hw_data->dtable = core->dtable;
> > +       div_hw_data->invalid_rate = core->invalid_rate;
> > +       div_hw_data->width = fls(max) - 1;
>
> Isn't that

My apologies for not finishing my sentence; I wanted to write "Isn't
that identical to __fls(max)?".  But as the latter generates slightly
worse code, it's not worth making that change.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds