[PATCH 5/7] arm64: dts: ti: k3-am62a: Add Wave5 Video Encoder/Decoder Node

[Brandon Brnich]

This patch adds support for the Wave521cl on the AM62A.

The node requires an SRAM buffer to reduce bandwidth by saving temporal
information. Can only allocate 62KB for this given there is only 64 KB
SRAM available on AM62A.

Wave521cl needs to use CMA as there is no IO MMU on AM62A. Allocate
544 MB of CMA to meet 12 channel 720x480 use-case for this device.

Signed-off-by: Brandon Brnich <b-brnich at ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 14 ++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62a7-sk.dts   | 12 ++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
index 4ae7fdc5221b..67eb1cc0ef6f 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
@@ -12,6 +12,10 @@ oc_sram: sram at 70000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x0 0x00 0x70000000 0x10000>;
+
+		vpu_sram: vpu-sram at 20000 {
+			reg = <0x20000 0xf800>;
+		};
 	};
 
 	gic500: interrupt-controller at 1800000 {
@@ -876,4 +880,14 @@ mcasp2: audio-controller at 2b20000 {
 		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
 		status = "disabled";
 	};
+
+	vpu: video-codec at 30210000 {
+		compatible = "cnm,cm521c-vpu";
+		reg = <0x00 0x30210000 0x00 0x10000>;
+		clocks = <&k3_clks 204 2>;
+		clock-names = "vcodec";
+		power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
+		sram = <&vpu_sram>;
+		status = "disabled";
+	};
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
index 8f64ac2c7568..b86aa20d50de 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
@@ -39,6 +39,14 @@ reserved-memory {
 		#size-cells = <2>;
 		ranges;
 
+		/* global cma region */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x00 0x24000000>;
+			linux,cma-default;
+		};
+
 		secure_tfa_ddr: tfa at 9e780000 {
 			reg = <0x00 0x9e780000 0x00 0x80000>;
 			alignment = <0x1000>;
@@ -458,6 +466,10 @@ &main_gpio_intr {
 	status = "okay";
 };
 
+&vpu {
+	status = "okay";
+};
+
 &main_uart0 {
 	status = "okay";
 	pinctrl-names = "default";
-- 
2.34.1