[RFC 4/6] media: verisilicon: Update H1 register definitions

[Chen-Yu Tsai]

On Thu, Nov 16, 2023 at 11:48 PM Andrzej Pietrasiewicz
<andrzej.p at collabora.com> wrote:
>
> Add definition of register at offset 0x00c.
>
> Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at collabora.com>
> ---
>  drivers/media/platform/verisilicon/hantro_h1_regs.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/media/platform/verisilicon/hantro_h1_regs.h b/drivers/media/platform/verisilicon/hantro_h1_regs.h
> index c1c66c934a24..efb46da23eab 100644
> --- a/drivers/media/platform/verisilicon/hantro_h1_regs.h
> +++ b/drivers/media/platform/verisilicon/hantro_h1_regs.h
> @@ -23,6 +23,15 @@
>  #define     H1_REG_AXI_CTRL_INPUT_SWAP32               BIT(2)
>  #define     H1_REG_AXI_CTRL_OUTPUT_SWAP8               BIT(1)
>  #define     H1_REG_AXI_CTRL_INPUT_SWAP8                        BIT(0)
> +#define H1_REG_DEVICE_CTRL                             0x00c
> +#define     H1_REG_DEVICE_CTRL_SCALE_OUTPUT_SWAP8      BIT(27)
> +#define     H1_REG_DEVICE_CTRL_SCALE_OUTPUT_SWAP16     BIT(26)
> +#define     H1_REG_DEVICE_CTRL_SCALE_OUTPUT_SWAP32     BIT(25)
> +#define     H1_REG_DEVICE_CTRL_MV_OUTPUT_SWAP8         BIT(24)
> +#define     H1_REG_DEVICE_CTRL_MV_OUTPUT_SWAP16                BIT(23)
> +#define     H1_REG_DEVICE_CTRL_MV_OUTPUT_SWAP32                BIT(22)
> +#define     H1_REG_DEVICE_CTRL_INPUT_READ_1MB          BIT(21)
> +#define     H1_REG_DEVICE_CTRL_AXI_DUAL_CHANNEL                BIT(20)

According to the i.MX8M Mini reference manual, this bit is a "disable"
control, i.e. setting this bit disables dual channel AXI. I think the
macro should explicitly state this in the naming, so something like
H1_REG_DEVICE_CTRL_DISABLE_AXI_DUAL_CH(ANNEL).

Other bits matches the reference manual.

>  #define H1_REG_ADDR_OUTPUT_STREAM                      0x014
>  #define H1_REG_ADDR_OUTPUT_CTRL                                0x018
>  #define H1_REG_ADDR_REF_LUMA                           0x01c
> --
> 2.25.1
>
>