[PATCH v4] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs.

[Marc Zyngier]

On Sun, 05 Nov 2023 08:55:11 +0000,
Thomas Gleixner <tglx at linutronix.de> wrote:
> 
> On Sat, Nov 04 2023 at 09:56, Marc Zyngier wrote:
> > On Mon, 30 Oct 2023 08:32:56 +0000,
> > Fang Xiang <fangxiang3 at xiaomi.com> wrote:
> >> 
> >> In non-coherent GIC design, ITS tables should be clean and flushed
> >> to the PoV of the ITS before writing GITS_BASER<n> registers, otherwise
> >> the ITS would read dirty tables and lead to UNPREDICTABLE behaviors.
> >> 
> >> The ITS always got clean tables in initialization with this fix, by
> >> observing the signals from GIC.
> >> 
> >> Furthermore, hoist the quirked non-shareable attributes earlier to
> >> save effort in tables setup.
> >> 
> >> Suggested-by: Marc Zyngier <maz at kernel.org>
> >> Signed-off-by: Fang Xiang <fangxiang3 at xiaomi.com>
> >> Tested-by: Fang Xiang <fangxiang3 at xiaomi.com>
> >
> > Reviewed-by: Marc Zyngier <maz at kernel.org>
> 
> Shouldn't this have a Fixes tag? My guess is:
> 
> a8707f553884 ("irqchip/gic-v3: Add Rockchip 3588001 erratum workaround")

Yes, that's indeed the point where the out of sequence programming can
occur.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.