[PATCH v4] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs.

[Marc Zyngier]

On Mon, 30 Oct 2023 08:32:56 +0000,
Fang Xiang <fangxiang3 at xiaomi.com> wrote:
> 
> In non-coherent GIC design, ITS tables should be clean and flushed
> to the PoV of the ITS before writing GITS_BASER<n> registers, otherwise
> the ITS would read dirty tables and lead to UNPREDICTABLE behaviors.
> 
> The ITS always got clean tables in initialization with this fix, by
> observing the signals from GIC.
> 
> Furthermore, hoist the quirked non-shareable attributes earlier to
> save effort in tables setup.
> 
> Suggested-by: Marc Zyngier <maz at kernel.org>
> Signed-off-by: Fang Xiang <fangxiang3 at xiaomi.com>
> Tested-by: Fang Xiang <fangxiang3 at xiaomi.com>

Reviewed-by: Marc Zyngier <maz at kernel.org>

	M.

-- 
Without deviation from the norm, progress is not possible.