[RFC] ACPI/irq: Apply ACPI_IRQCHIP_FWSPEC_ARG0 only for GSI domain

[Shanker Donthineni]

Hi James

When the IRQ combining feature is enabled, the following modification becomes
necessary. Without implementing this change. The MPAM feature is not working on
NVIDIA platforms.

Please review the code and provide feedback.


On 4/28/23 11:58, Shanker Donthineni wrote:
> The implementation of the updated GICv3 parameter parsing code in
> pack_fwspec() is not compatible for the non-GSI drivers. It uses
> the offset 1 for hardware IRQ, but the unmodified GPIO driver
> expects the offset value to be 0, leading to a regression.
> 
> This patch applies new mapping to the GSI driver only to fix
> the issue.
> 
> Signed-off-by: Shanker Donthineni <sdonthineni at nvidia.com>
> ---
> 
>   drivers/acpi/irq.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c
> index d4225d0b45d0..3d7f0643ed14 100644
> --- a/drivers/acpi/irq.c
> +++ b/drivers/acpi/irq.c
> @@ -53,7 +53,8 @@ static void pack_fwspec(struct irq_fwspec *fwspec, u32 gsi, int trigger,
>   {
>   	unsigned int offset = 0;
>   
> -	if (IS_ENABLED(CONFIG_ACPI_IRQCHIP_FWSPEC_ARG0)) {
> +	if (IS_ENABLED(CONFIG_ACPI_IRQCHIP_FWSPEC_ARG0) &&
> +	    (fwspec->fwnode == acpi_get_gsi_domain_id(gsi))) {
>   		fwspec->param[0] = ACPI_IRQCHIP_FWSPEC_ARG0;
>   		offset = 1;
>   	}
> @@ -216,8 +217,8 @@ static inline void acpi_irq_parse_one_match(struct fwnode_handle *fwnode,
>   	ctx->rc = 0;
>   	*ctx->res_flags = acpi_dev_irq_flags(triggering, polarity, shareable, wake_capable);
>   
> -	pack_fwspec(ctx->fwspec, hwirq, triggering, polarity);
>   	ctx->fwspec->fwnode = fwnode;
> +	pack_fwspec(ctx->fwspec, hwirq, triggering, polarity);
>   }
>   
>   /**