[PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones

[AngeloGioacchino Del Regno]

Il 29/05/23 18:46, Bernhard Rosenkränzer ha scritto:
> From: Balsam CHIHI <bchihi at baylibre.com>
> 
> Add thermal nodes and thermal zones for the mt8192.
> The mt8192 SoC has several hotspots around the CPUs.
> Specify the targeted temperature threshold to apply the mitigation
> and define the associated cooling devices.
> 
> Signed-off-by: Balsam CHIHI <bchihi at baylibre.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado at collabora.com>
> [bero at baylibre.com: cosmetic changes]
> Signed-off-by: Bernhard Rosenkränzer <bero at baylibre.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 +++++++++++++++++++++++
>   1 file changed, 454 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 5c30caf740265..330c5bb4ebc85 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -14,6 +14,8 @@
>   #include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
>   #include <dt-bindings/reset/mt8192-resets.h>
> +#include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
>   
>   / {
>   	compatible = "mediatek,mt8192";
> @@ -71,6 +73,7 @@ cpu0: cpu at 0 {
>   			d-cache-sets = <128>;
>   			next-level-cache = <&l2_0>;
>   			capacity-dmips-mhz = <530>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu1: cpu at 100 {
> @@ -88,6 +91,7 @@ cpu1: cpu at 100 {
>   			d-cache-sets = <128>;
>   			next-level-cache = <&l2_0>;
>   			capacity-dmips-mhz = <530>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu2: cpu at 200 {
> @@ -105,6 +109,7 @@ cpu2: cpu at 200 {
>   			d-cache-sets = <128>;
>   			next-level-cache = <&l2_0>;
>   			capacity-dmips-mhz = <530>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu3: cpu at 300 {
> @@ -122,6 +127,7 @@ cpu3: cpu at 300 {
>   			d-cache-sets = <128>;
>   			next-level-cache = <&l2_0>;
>   			capacity-dmips-mhz = <530>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu4: cpu at 400 {
> @@ -139,6 +145,7 @@ cpu4: cpu at 400 {
>   			d-cache-sets = <256>;
>   			next-level-cache = <&l2_1>;
>   			capacity-dmips-mhz = <1024>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu5: cpu at 500 {
> @@ -156,6 +163,7 @@ cpu5: cpu at 500 {
>   			d-cache-sets = <256>;
>   			next-level-cache = <&l2_1>;
>   			capacity-dmips-mhz = <1024>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu6: cpu at 600 {
> @@ -173,6 +181,7 @@ cpu6: cpu at 600 {
>   			d-cache-sets = <256>;
>   			next-level-cache = <&l2_1>;
>   			capacity-dmips-mhz = <1024>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu7: cpu at 700 {
> @@ -190,6 +199,7 @@ cpu7: cpu at 700 {
>   			d-cache-sets = <256>;
>   			next-level-cache = <&l2_1>;
>   			capacity-dmips-mhz = <1024>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu-map {
> @@ -771,6 +781,17 @@ spi0: spi at 1100a000 {
>   			status = "disabled";
>   		};
>   
> +		lvts_ap: thermal-sensor at 1100b000 {
> +			compatible = "mediatek,mt8192-lvts-ap";
> +			reg = <0 0x1100b000 0 0x1000>;

reg = <0 0x1100b000 0 0xc00>;

...as 0xc00 should be more than sufficient. This is important for later
when we'll get SVS support up (which is in the LVTS-AP iospace range).

Regards,
Angelo